Unverified Commit 847689d2 authored by Alexandre Ghiti's avatar Alexandre Ghiti Committed by Palmer Dabbelt
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Merge patch series "riscv: Add Zicbop & prefetchw support" 

Alexandre Ghiti <alexghiti@rivosinc.com> says:

I found this lost series developed by Guo so here is a respin with the
comments on v2 applied.

This patch series adds Zicbop support and then enables the Linux
prefetch features.

* patches from https://lore.kernel.org/r/20250421142441.395849-1-alexghiti@rivosinc.com:
  riscv: xchg: Prefetch the destination word for sc.w
  riscv: Add ARCH_HAS_PREFETCH[W] support with Zicbop
  riscv: Add support for Zicbop
  riscv: Introduce Zicbop instructions

Link: https://lore.kernel.org/r/20250421142441.395849-1-alexghiti@rivosinc.com


Signed-off-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@dabbelt.com>
parents 415a8c81 eb87e56d

arch/riscv/Kconfig

+15 −0
Original line number Diff line number Diff line
@@ -847,6 +847,21 @@ config RISCV_ISA_ZICBOZ 


	   If you don't know what to do here, say Y.



config RISCV_ISA_ZICBOP

	bool "Zicbop extension support for cache block prefetch"

	depends on MMU

	depends on RISCV_ALTERNATIVE

	default y

	help

	  Adds support to dynamically detect the presence of the ZICBOP

	  extension (Cache Block Prefetch Operations) and enable its

	  usage.



	  The Zicbop extension can be used to prefetch cache blocks for

	  read/write fetch.



	  If you don't know what to do here, say Y.



config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI

	def_bool y

	# https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc

arch/riscv/include/asm/barrier.h

+0 −5
Original line number Diff line number Diff line
@@ -14,11 +14,6 @@ 
#include <asm/cmpxchg.h>

#include <asm/fence.h>



#define nop()		__asm__ __volatile__ ("nop")

#define __nops(n)	".rept	" #n "\nnop\n.endr\n"

#define nops(n)		__asm__ __volatile__ (__nops(n))





/* These barriers need to enforce ordering on both devices or memory. */

#define __mb()		RISCV_FENCE(iorw, iorw)

#define __rmb()		RISCV_FENCE(ir, ir)

arch/riscv/include/asm/cacheflush.h

+1 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ void flush_icache_mm(struct mm_struct *mm, bool local); 


extern unsigned int riscv_cbom_block_size;

extern unsigned int riscv_cboz_block_size;

extern unsigned int riscv_cbop_block_size;

void riscv_init_cbo_blocksizes(void);



#ifdef CONFIG_RISCV_DMA_NONCOHERENT

arch/riscv/include/asm/cmpxchg.h

+3 −1
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <asm/hwcap.h>

#include <asm/insn-def.h>

#include <asm/cpufeature-macros.h>

#include <asm/processor.h>



#define __arch_xchg_masked(sc_sfx, swap_sfx, prepend, sc_append,		\

			   swap_append, r, p, n)				\
@@ -37,6 +38,7 @@ 
										\

		__asm__ __volatile__ (						\

		       prepend							\

		       PREFETCHW_ASM(%5)					\

		       "0:	lr.w %0, %2\n"					\

		       "	and  %1, %0, %z4\n"				\

		       "	or   %1, %1, %z3\n"				\
@@ -44,7 +46,7 @@ 
		       "	bnez %1, 0b\n"					\

		       sc_append						\

		       : "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b))	\

		       : "rJ" (__newx), "rJ" (~__mask)				\

		       : "rJ" (__newx), "rJ" (~__mask), "rJ" (__ptr32b)		\

		       : "memory");						\

										\

		r = (__typeof__(*(p)))((__retx & __mask) >> __s);		\

arch/riscv/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ 
#define RISCV_ISA_EXT_ZVFBFWMA		96

#define RISCV_ISA_EXT_ZAAMO		97

#define RISCV_ISA_EXT_ZALRSC		98

#define RISCV_ISA_EXT_ZICBOP		99



#define RISCV_ISA_EXT_XLINUXENVCFG	127