Commit 84bf82f4 authored by Harish Chegondi's avatar Harish Chegondi Committed by Matt Roper
Browse files

drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+ 



Xe_LPG+ (IP version 12.74) should take the same general code
paths as Xe_LPG (versions 12.70 and 12.71).

Xe_LPG+'s workaround list will be handled by the next patch.

Signed-off-by: default avatarHarish Chegondi <harish.chegondi@intel.com>
Signed-off-by: default avatarHaridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240108122738.14399-3-haridhar.kalvala@intel.com
parent 28478147

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+2 −1
Original line number Diff line number Diff line
@@ -1190,7 +1190,8 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine) 
			num = ARRAY_SIZE(xelpmp_regs);

		}

	} else {

		if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||

		if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 74) ||

		    GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||

		    GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||

		    GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||

		    GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {

drivers/gpu/drm/i915/gt/intel_mocs.c

+1 −1
Original line number Diff line number Diff line
@@ -495,7 +495,7 @@ static unsigned int get_mocs_settings(struct drm_i915_private *i915, 
	memset(table, 0, sizeof(struct drm_i915_mocs_table));



	table->unused_entries_index = I915_MOCS_PTE;

	if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {

	if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) {

		table->size = ARRAY_SIZE(mtl_mocs_table);

		table->table = mtl_mocs_table;

		table->n_entries = MTL_NUM_MOCS_ENTRIES;

drivers/gpu/drm/i915/gt/intel_rc6.c

+1 −1
Original line number Diff line number Diff line
@@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) 
	 * temporary wa and should be removed after fixing real cause

	 * of forcewake timeouts.

	 */

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))

		pg_enable =

			GEN9_MEDIA_PG_ENABLE |

			GEN11_MEDIA_SAMPLER_PG_ENABLE;

drivers/gpu/drm/i915/i915_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj) 
{

	struct drm_i915_private *i915 = obj_to_i915(obj);



	if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {

	if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) {

		switch (obj->pat_index) {

		case 0: return " WB";

		case 1: return " WT";