Commit 84d2d043 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/color: Extract intel_color_modeset() 



We always perform the same steps to program color management
stuff during a full modeset. Extract that code to a helper
to avoid duplication.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240916152958.17332-2-ville.syrjala@linux.intel.com


Reviewed-by: default avatarLuca Coelho <luciano.coelho@intel.com>
parent ae5d0397

drivers/gpu/drm/i915/display/intel_color.c

+17 −0
Original line number Diff line number Diff line
@@ -1902,6 +1902,23 @@ void intel_color_post_update(const struct intel_crtc_state *crtc_state) 
		i915->display.funcs.color->color_post_update(crtc_state);

}



void intel_color_modeset(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);



	intel_color_load_luts(crtc_state);

	intel_color_commit_noarm(crtc_state);

	intel_color_commit_arm(crtc_state);



	if (DISPLAY_VER(display) < 9) {

		struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

		struct intel_plane *plane = to_intel_plane(crtc->base.primary);



		/* update DSPCNTR to configure gamma/csc for pipe bottom color */

		plane->disable_arm(plane, crtc_state);

	}

}



void intel_color_prepare_commit(struct intel_atomic_state *state,

				struct intel_crtc *crtc)

{

drivers/gpu/drm/i915/display/intel_color.h

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state); 
void intel_color_commit_arm(const struct intel_crtc_state *crtc_state);

void intel_color_post_update(const struct intel_crtc_state *crtc_state);

void intel_color_load_luts(const struct intel_crtc_state *crtc_state);

void intel_color_modeset(const struct intel_crtc_state *crtc_state);

void intel_color_get_config(struct intel_crtc_state *crtc_state);

bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,

			   const struct drm_property_blob *blob1,

drivers/gpu/drm/i915/display/intel_display.c

+4 −29
Original line number Diff line number Diff line
@@ -1563,14 +1563,6 @@ static void intel_encoders_update_pipe(struct intel_atomic_state *state, 
	}

}



static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct intel_plane *plane = to_intel_plane(crtc->base.primary);



	plane->disable_arm(plane, crtc_state);

}



static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1636,11 +1628,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state, 
	 * On ILK+ LUT must be loaded before the pipe is running but with

	 * clocks enabled

	 */

	intel_color_load_luts(new_crtc_state);

	intel_color_commit_noarm(new_crtc_state);

	intel_color_commit_arm(new_crtc_state);

	/* update DSPCNTR to configure gamma for pipe bottom color */

	intel_disable_primary_plane(new_crtc_state);

	intel_color_modeset(new_crtc_state);



	intel_initial_watermarks(state, crtc);

	intel_enable_transcoder(new_crtc_state);
@@ -1799,12 +1787,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, 
		 * On ILK+ LUT must be loaded before the pipe is running but with

		 * clocks enabled

		 */

		intel_color_load_luts(pipe_crtc_state);

		intel_color_commit_noarm(pipe_crtc_state);

		intel_color_commit_arm(pipe_crtc_state);

		/* update DSPCNTR to configure gamma/csc for pipe bottom color */

		if (DISPLAY_VER(dev_priv) < 9)

			intel_disable_primary_plane(pipe_crtc_state);

		intel_color_modeset(pipe_crtc_state);



		hsw_set_linetime_wm(pipe_crtc_state);
@@ -2203,11 +2186,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, 


	i9xx_pfit_enable(new_crtc_state);



	intel_color_load_luts(new_crtc_state);

	intel_color_commit_noarm(new_crtc_state);

	intel_color_commit_arm(new_crtc_state);

	/* update DSPCNTR to configure gamma for pipe bottom color */

	intel_disable_primary_plane(new_crtc_state);

	intel_color_modeset(new_crtc_state);



	intel_initial_watermarks(state, crtc);

	intel_enable_transcoder(new_crtc_state);
@@ -2243,11 +2222,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state, 


	i9xx_pfit_enable(new_crtc_state);



	intel_color_load_luts(new_crtc_state);

	intel_color_commit_noarm(new_crtc_state);

	intel_color_commit_arm(new_crtc_state);

	/* update DSPCNTR to configure gamma for pipe bottom color */

	intel_disable_primary_plane(new_crtc_state);

	intel_color_modeset(new_crtc_state);



	if (!intel_initial_watermarks(state, crtc))

		intel_update_watermarks(dev_priv);