Commit 8568b3c4 authored by Shenwei Wang's avatar Shenwei Wang Committed by Abel Vesa
Browse files

clk: imx: imx8qxp: correct the enet clocks for i.MX8DXL 



The SC_PM_CLK_MISC0 clock is not available for the resources of ENET0/1 on
i.MX8DXL. Using the clock device compatible string to identify the platform
and only initialize the enetX_rgmii_rx_clk clock for non i.MX8DXL platform.

Signed-off-by: default avatarShenwei Wang <shenwei.wang@nxp.com>
Reviewed-by: default avatarRanjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Reviewed-by: default avatarJacky Bai <ping.bai@nxp.com>
Acked-by: default avatarJason Liu <jason.hui.liu@nxp.com>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230912-imx8-clk-v1-v1-3-69a34bcfcae1@nxp.com


Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
parent 15cee75d

drivers/clk/imx/clk-imx8qxp.c

+9 −2
Original line number Diff line number Diff line
@@ -90,6 +90,11 @@ static const char * const pi_pll0_sels[] = { 
	"clk_dummy",

};



static inline bool clk_on_imx8dxl(struct device_node *node)

{

	return of_device_is_compatible(node, "fsl,imx8dxl-clk");

}



static int imx8qxp_clk_probe(struct platform_device *pdev)

{

	struct device_node *ccm_node = pdev->dev.of_node;
@@ -169,13 +174,15 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) 
	imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK);

	imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);

	imx_clk_gate_gpr_scu("enet0_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true);

	if (!clk_on_imx8dxl(ccm_node)) {

		imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);

		imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);

	}

	imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);

	imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV);

	imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK);

	imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);

	imx_clk_gate_gpr_scu("enet1_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true);

	imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);

	imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);

	imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);

	imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);