Commit 860b0cf5 authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
Browse files

drm/amd/display: move trace buffer to uncached memory. 



[Why & How]
Move dmub trace buffer to uncached memory.

Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: default avatarBindu Ramamurthy <bindu.r@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 349a19b2

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

+7 −0
Original line number Diff line number Diff line
@@ -248,6 +248,13 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub, 
		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,

		  DMCUB_REGION3_CW5_ENABLE, 1);



	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);

	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);

	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,

		  DMCUB_REGION5_TOP_ADDRESS,

		  cw5->region.top - cw5->region.base - 1,

		  DMCUB_REGION5_ENABLE, 1);



	dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);



	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

+7 −0
Original line number Diff line number Diff line
@@ -75,6 +75,9 @@ struct dmub_srv; 
	DMUB_SR(DMCUB_REGION4_OFFSET) \

	DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \

	DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \

	DMUB_SR(DMCUB_REGION5_OFFSET) \

	DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \

	DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \

	DMUB_SR(DMCUB_SCRATCH0) \

	DMUB_SR(DMCUB_SCRATCH1) \

	DMUB_SR(DMCUB_SCRATCH2) \
@@ -123,6 +126,8 @@ struct dmub_srv; 
	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \

	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \

	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \

	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \

	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \

	DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \

	DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \

	DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
@@ -200,4 +205,6 @@ union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub); 


bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub);



bool dmub_dcn20_use_cached_trace_buffer(struct dmub_srv *dmub);



#endif /* _DMUB_DCN20_H_ */

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

+7 −0
Original line number Diff line number Diff line
@@ -180,6 +180,13 @@ void dmub_dcn30_setup_windows(struct dmub_srv *dmub, 
		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,

		  DMCUB_REGION3_CW5_ENABLE, 1);



	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);

	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);

	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,

		  DMCUB_REGION5_TOP_ADDRESS,

		  cw5->region.top - cw5->region.base - 1,

		  DMCUB_REGION5_ENABLE, 1);



	offset = cw6->offset;



	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);