Commit 863fb752 authored by Nícolas F. R. A. Prado's avatar Nícolas F. R. A. Prado Committed by Matthias Brugger
Browse files

arm64: dts: mediatek: asurada: Add Cr50 TPM 



The Asurada platform has a Google Security Chip connected to the SPI5
bus. It runs the cr50 firmware and provides TPM functionality. Add
support for it.

Signed-off-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220629155956.1138955-10-nfraprado@collabora.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 9b909db6

arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
 */

/dts-v1/;

#include "mt8192.dtsi"

#include <dt-bindings/gpio/gpio.h>



/ {

	aliases {
@@ -353,6 +354,13 @@ &pio { 
			  "AUD_DAT_MISO0",

			  "AUD_DAT_MISO1";



	cr50_int: cr50-irq-default-pins {

		pins-gsc-ap-int-odl {

			pinmux = <PINMUX_GPIO171__FUNC_GPIO171>;

			input-enable;

		};

	};



	cros_ec_int: cros-ec-irq-default-pins {

		pins-ec-ap-int-odl {

			pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
@@ -513,6 +521,15 @@ &spi5 { 
	mediatek,pad-select = <0>;

	pinctrl-names = "default";

	pinctrl-0 = <&spi5_pins>;



	cr50@0 {

		compatible = "google,cr50";

		reg = <0>;

		interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>;

		spi-max-frequency = <1000000>;

		pinctrl-names = "default";

		pinctrl-0 = <&cr50_int>;

	};

};



&uart0 {