Commit 86ef6eae authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
Browse files

drm/amdgpu/sdma6: add aggregated doorbell support 



Port aggregated doorbell support to sdma6.

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2d7a1f71

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

+57 −23
Original line number Diff line number Diff line
@@ -246,8 +246,39 @@ static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 
static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	uint32_t *wptr_saved;

	uint32_t *is_queue_unmap;

	uint64_t aggregated_db_index;

	uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;



	DRM_DEBUG("Setting write pointer\n");



	if (ring->is_mes_queue) {

		wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);

		is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +

					      sizeof(uint32_t));

		aggregated_db_index =

			amdgpu_mes_get_aggregated_doorbell_index(adev,

							 ring->hw_prio);



		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,

			     ring->wptr << 2);

		*wptr_saved = ring->wptr << 2;

		if (*is_queue_unmap) {

			WDOORBELL64(aggregated_db_index, ring->wptr << 2);

			DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",

					ring->doorbell_index, ring->wptr << 2);

			WDOORBELL64(ring->doorbell_index, ring->wptr << 2);

		} else {

			DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",

					ring->doorbell_index, ring->wptr << 2);

			WDOORBELL64(ring->doorbell_index, ring->wptr << 2);



			if (*is_queue_unmap)

				WDOORBELL64(aggregated_db_index,

					    ring->wptr << 2);

		}

	} else {

		if (ring->use_doorbell) {

			DRM_DEBUG("Using doorbell -- "

				  "wptr_offs == 0x%08x "
@@ -270,12 +301,15 @@ static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 
				  lower_32_bits(ring->wptr << 2),

				  ring->me,

				  upper_32_bits(ring->wptr << 2));

		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, ring->me, regSDMA0_QUEUE0_RB_WPTR),

			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,

				        ring->me, regSDMA0_QUEUE0_RB_WPTR),

					lower_32_bits(ring->wptr << 2));

		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, ring->me, regSDMA0_QUEUE0_RB_WPTR_HI),

			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,

				        ring->me, regSDMA0_QUEUE0_RB_WPTR_HI),

					upper_32_bits(ring->wptr << 2));

		}

	}

}



static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

{