Commit 870d1e5a authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Fix interrupt handling in GFX v9.4.3 



IH follows a different identification scheme for its clients. Get the
right mapping of xcc instance from IH node id.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarLe Ma <le.ma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 369576c2

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

+30 −5
Original line number Diff line number Diff line
@@ -2730,11 +2730,24 @@ static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 
	return 0;

}



static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)

{

	int xcc;



	xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0));

	if (!xcc) {

		dev_err(adev->dev, "Couldn't find xcc mapping from IH node");

		return -EINVAL;

	}



	return xcc - 1;

}



static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev,

			    struct amdgpu_irq_src *source,

			    struct amdgpu_iv_entry *entry)

{

	int i, phys_id;

	int i, xcc_id;

	u8 me_id, pipe_id, queue_id;

	struct amdgpu_ring *ring;
@@ -2743,14 +2756,19 @@ static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 
	pipe_id = (entry->ring_id & 0x03) >> 0;

	queue_id = (entry->ring_id & 0x70) >> 4;



	phys_id = node_id_to_phys_map[entry->node_id];

	xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);



	if (xcc_id == -EINVAL)

		return -EINVAL;



	switch (me_id) {

	case 0:

	case 1:

	case 2:

		for (i = 0; i < adev->gfx.num_compute_rings; i++) {

			ring = &adev->gfx.compute_ring[i + phys_id * adev->gfx.num_compute_rings];

			ring = &adev->gfx.compute_ring

					[i +

					 xcc_id * adev->gfx.num_compute_rings];

			/* Per-queue interrupt is supported for MEC starting from VI.

			  * The interrupt can only be enabled/disabled per pipe instead of per queue.

			  */
@@ -2768,18 +2786,25 @@ static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 
{

	u8 me_id, pipe_id, queue_id;

	struct amdgpu_ring *ring;

	int i;

	int i, xcc_id;



	me_id = (entry->ring_id & 0x0c) >> 2;

	pipe_id = (entry->ring_id & 0x03) >> 0;

	queue_id = (entry->ring_id & 0x70) >> 4;



	xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);



	if (xcc_id == -EINVAL)

		return;



	switch (me_id) {

	case 0:

	case 1:

	case 2:

		for (i = 0; i < adev->gfx.num_compute_rings; i++) {

			ring = &adev->gfx.compute_ring[i];

			ring = &adev->gfx.compute_ring

					[i +

					 xcc_id * adev->gfx.num_compute_rings];

			if (ring->me == me_id && ring->pipe == pipe_id &&

			    ring->queue == queue_id)

				drm_sched_fault(&ring->sched);