Commit 8839d1cc authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-mlx5-misc-changes-2025-07-21' 

Tariq Toukan says:

====================
net/mlx5: misc changes 2025-07-21

This series by Lama contains misc enhancements to the SHAMPO parameters.
====================

Link: https://patch.msgid.link/1753081999-326247-1-git-send-email-tariqt@nvidia.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents ad892e91 eeaf1146

drivers/net/ethernet/mellanox/mlx5/core/en.h

+5 −5
Original line number Diff line number Diff line
@@ -84,9 +84,10 @@ struct page_pool; 
#define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9)

#define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)

#define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE (PAGE_SHIFT - MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)

#define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64)

#define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024)

#define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096)

#define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE_SHIFT (6)

#define MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT (12)

#define MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE (16)

#define MLX5E_SHAMPO_WQ_RESRV_SIZE BIT(MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE)



#define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \

	(6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
@@ -629,14 +630,13 @@ struct mlx5e_dma_info { 
};



struct mlx5e_shampo_hd {

	u32 mkey;

	struct mlx5e_frag_page *pages;

	u32 hd_per_wq;

	u16 hd_per_wqe;

	unsigned long *bitmap;

	u16 pi;

	u16 ci;

	__be32 key;

	__be32 mkey_be;

};



struct mlx5e_hw_gro_data {

drivers/net/ethernet/mellanox/mlx5/core/en/params.c

+15 −30
Original line number Diff line number Diff line
@@ -414,25 +414,10 @@ u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5_core_dev *mdev, 
	return params->log_rq_mtu_frames - log_pkts_per_wqe;

}



u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev,

				      struct mlx5e_params *params)

{

	return order_base_2(DIV_ROUND_UP(MLX5E_RX_MAX_HEAD, MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE));

}



u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev,

				  struct mlx5e_params *params)

static u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5e_params *params)

{

	return order_base_2(MLX5E_SHAMPO_WQ_RESRV_SIZE / MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE);

}



u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev,

				     struct mlx5e_params *params)

{

	u32 resrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) *

			 MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE;



	return order_base_2(DIV_ROUND_UP(resrv_size, params->sw_mtu));

	return order_base_2(DIV_ROUND_UP(MLX5E_SHAMPO_WQ_RESRV_SIZE,

					 params->sw_mtu));

}



u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
@@ -834,13 +819,12 @@ static u32 mlx5e_shampo_get_log_cq_size(struct mlx5_core_dev *mdev, 
					struct mlx5e_params *params,

					struct mlx5e_xsk_param *xsk)

{

	int rsrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) *

		MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE;

	u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));

	int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params));

	u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);

	int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(params));

	int wq_size = BIT(mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk));

	int wqe_size = BIT(log_stride_sz) * num_strides;

	int rsrv_size = MLX5E_SHAMPO_WQ_RESRV_SIZE;



	/* +1 is for the case that the pkt_per_rsrv dont consume the reservation

	 * so we get a filler cqe for the rest of the reservation.
@@ -932,12 +916,14 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, 


		MLX5_SET(wq, wq, shampo_enable, true);

		MLX5_SET(wq, wq, log_reservation_size,

			 mlx5e_shampo_get_log_rsrv_size(mdev, params));

			 MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE -

			 MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT);

		MLX5_SET(wq, wq,

			 log_max_num_of_packets_per_reservation,

			 mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params));

			 mlx5e_shampo_get_log_pkt_per_rsrv(params));

		MLX5_SET(wq, wq, log_headers_entry_size,

			 mlx5e_shampo_get_log_hd_entry_size(mdev, params));

			 MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE -

			 MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE_SHIFT);

		lro_timeout =

			mlx5e_choose_lro_timeout(mdev,

						 MLX5E_DEFAULT_SHAMPO_TIMEOUT);
@@ -1048,18 +1034,17 @@ u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev, 
			    struct mlx5e_params *params,

			    struct mlx5e_rq_param *rq_param)

{

	int resv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) *

		MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE;

	u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, NULL));

	int pkt_per_resv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params));

	u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL);

	int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(params));

	int wqe_size = BIT(log_stride_sz) * num_strides;

	int rsrv_size = MLX5E_SHAMPO_WQ_RESRV_SIZE;

	u32 hd_per_wqe;



	/* Assumption: hd_per_wqe % 8 == 0. */

	hd_per_wqe = (wqe_size / resv_size) * pkt_per_resv;

	mlx5_core_dbg(mdev, "%s hd_per_wqe = %d rsrv_size = %d wqe_size = %d pkt_per_resv = %d\n",

		      __func__, hd_per_wqe, resv_size, wqe_size, pkt_per_resv);

	hd_per_wqe = (wqe_size / rsrv_size) * pkt_per_rsrv;

	mlx5_core_dbg(mdev, "%s hd_per_wqe = %d rsrv_size = %d wqe_size = %d pkt_per_rsrv = %d\n",

		      __func__, hd_per_wqe, rsrv_size, wqe_size, pkt_per_rsrv);

	return hd_per_wqe;

}

drivers/net/ethernet/mellanox/mlx5/core/en/params.h

+0 −6
Original line number Diff line number Diff line
@@ -95,12 +95,6 @@ bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev, 
u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5_core_dev *mdev,

			       struct mlx5e_params *params,

			       struct mlx5e_xsk_param *xsk);

u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev,

				      struct mlx5e_params *params);

u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev,

				  struct mlx5e_params *params);

u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev,

				     struct mlx5e_params *params);

u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev,

			    struct mlx5e_params *params,

			    struct mlx5e_rq_param *rq_param);

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+18 −9
Original line number Diff line number Diff line
@@ -546,18 +546,26 @@ static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq 
}



static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,

				       u16 hd_per_wq, u32 *umr_mkey)

				       u16 hd_per_wq, __be32 *umr_mkey)

{

	u32 max_ksm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));

	u32 mkey;

	int err;



	if (max_ksm_size < hd_per_wq) {

		mlx5_core_err(mdev, "max ksm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",

			      max_ksm_size, hd_per_wq);

		return -EINVAL;

	}

	return mlx5e_create_umr_ksm_mkey(mdev, hd_per_wq,



	err = mlx5e_create_umr_ksm_mkey(mdev, hd_per_wq,

					MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE,

					 umr_mkey);

					&mkey);

	if (err)

		return err;



	*umr_mkey = cpu_to_be32(mkey);

	return 0;

}



static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
@@ -783,11 +791,10 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev, 
		goto err_shampo_hd_info_alloc;



	err = mlx5e_create_rq_hd_umr_mkey(mdev, hd_per_wq,

					  &rq->mpwqe.shampo->mkey);

					  &rq->mpwqe.shampo->mkey_be);

	if (err)

		goto err_umr_mkey;



	rq->mpwqe.shampo->key = cpu_to_be32(rq->mpwqe.shampo->mkey);

	rq->mpwqe.shampo->hd_per_wqe =

		mlx5e_shampo_hd_per_wqe(mdev, params, rqp);

	wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
@@ -832,7 +839,7 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev, 
err_hw_gro_data:

	page_pool_destroy(rq->hd_page_pool);

err_hds_page_pool:

	mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey);

	mlx5_core_destroy_mkey(mdev, be32_to_cpu(rq->mpwqe.shampo->mkey_be));

err_umr_mkey:

	mlx5e_rq_shampo_hd_info_free(rq);

err_shampo_hd_info_alloc:
@@ -849,7 +856,8 @@ static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq) 
	if (rq->hd_page_pool != rq->page_pool)

		page_pool_destroy(rq->hd_page_pool);

	mlx5e_rq_shampo_hd_info_free(rq);

	mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey);

	mlx5_core_destroy_mkey(rq->mdev,

			       be32_to_cpu(rq->mpwqe.shampo->mkey_be));

	kvfree(rq->mpwqe.shampo);

}
@@ -1122,7 +1130,8 @@ int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16 q_cou 
	if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {

		MLX5_SET(wq, wq, log_headers_buffer_entry_num,

			 order_base_2(rq->mpwqe.shampo->hd_per_wq));

		MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);

		MLX5_SET(wq, wq, headers_mkey,

			 be32_to_cpu(rq->mpwqe.shampo->mkey_be));

	}



	mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,

drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

+1 −1
Original line number Diff line number Diff line
@@ -676,7 +676,7 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *rq, 
	wqe_bbs = MLX5E_KSM_UMR_WQEBBS(ksm_entries);

	pi = mlx5e_icosq_get_next_pi(sq, wqe_bbs);

	umr_wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi);

	build_ksm_umr(sq, umr_wqe, shampo->key, index, ksm_entries);

	build_ksm_umr(sq, umr_wqe, shampo->mkey_be, index, ksm_entries);



	WARN_ON_ONCE(ksm_entries & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1));

	while (i < ksm_entries) {