Commit 88436dec authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/wm: move wm state verification to intel_pm.c 



By moving wm state verification to intel_pm.c, we can make a bunch of
functions static, hiding the wm details better. Also declutter
intel_display.c.

v2: intel_wm_state_verify -> intel_wm_verify_state (Ville)

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2a7e3141e87181c07eaddcd9c352b8810550b0ce.1655372759.git.jani.nikula@intel.com
parent d36bdd77

drivers/gpu/drm/i915/display/intel_display.c

+1 −121
Original line number Diff line number Diff line
@@ -6424,126 +6424,6 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, 
	}

}



static void verify_wm_state(struct intel_crtc *crtc,

			    struct intel_crtc_state *new_crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct skl_hw_state {

		struct skl_ddb_entry ddb[I915_MAX_PLANES];

		struct skl_ddb_entry ddb_y[I915_MAX_PLANES];

		struct skl_pipe_wm wm;

	} *hw;

	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;

	int level, max_level = ilk_wm_max_level(dev_priv);

	struct intel_plane *plane;

	u8 hw_enabled_slices;



	if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active)

		return;



	hw = kzalloc(sizeof(*hw), GFP_KERNEL);

	if (!hw)

		return;



	skl_pipe_wm_get_hw_state(crtc, &hw->wm);



	skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);



	hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);



	if (DISPLAY_VER(dev_priv) >= 11 &&

	    hw_enabled_slices != dev_priv->dbuf.enabled_slices)

		drm_err(&dev_priv->drm,

			"mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",

			dev_priv->dbuf.enabled_slices,

			hw_enabled_slices);



	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {

		const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;

		const struct skl_wm_level *hw_wm_level, *sw_wm_level;



		/* Watermarks */

		for (level = 0; level <= max_level; level++) {

			hw_wm_level = &hw->wm.planes[plane->id].wm[level];

			sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);



			if (skl_wm_level_equals(hw_wm_level, sw_wm_level))

				continue;



			drm_err(&dev_priv->drm,

				"[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",

				plane->base.base.id, plane->base.name, level,

				sw_wm_level->enable,

				sw_wm_level->blocks,

				sw_wm_level->lines,

				hw_wm_level->enable,

				hw_wm_level->blocks,

				hw_wm_level->lines);

		}



		hw_wm_level = &hw->wm.planes[plane->id].trans_wm;

		sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);



		if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {

			drm_err(&dev_priv->drm,

				"[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",

				plane->base.base.id, plane->base.name,

				sw_wm_level->enable,

				sw_wm_level->blocks,

				sw_wm_level->lines,

				hw_wm_level->enable,

				hw_wm_level->blocks,

				hw_wm_level->lines);

		}



		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;

		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;



		if (HAS_HW_SAGV_WM(dev_priv) &&

		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {

			drm_err(&dev_priv->drm,

				"[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",

				plane->base.base.id, plane->base.name,

				sw_wm_level->enable,

				sw_wm_level->blocks,

				sw_wm_level->lines,

				hw_wm_level->enable,

				hw_wm_level->blocks,

				hw_wm_level->lines);

		}



		hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;

		sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;



		if (HAS_HW_SAGV_WM(dev_priv) &&

		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {

			drm_err(&dev_priv->drm,

				"[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",

				plane->base.base.id, plane->base.name,

				sw_wm_level->enable,

				sw_wm_level->blocks,

				sw_wm_level->lines,

				hw_wm_level->enable,

				hw_wm_level->blocks,

				hw_wm_level->lines);

		}



		/* DDB */

		hw_ddb_entry = &hw->ddb[PLANE_CURSOR];

		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];



		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {

			drm_err(&dev_priv->drm,

				"[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",

				plane->base.base.id, plane->base.name,

				sw_ddb_entry->start, sw_ddb_entry->end,

				hw_ddb_entry->start, hw_ddb_entry->end);

		}

	}



	kfree(hw);

}



static void

verify_connector_state(struct intel_atomic_state *state,

		       struct intel_crtc *crtc)
@@ -6836,7 +6716,7 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc, 
	if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)

		return;



	verify_wm_state(crtc, new_crtc_state);

	intel_wm_state_verify(crtc, new_crtc_state);

	verify_connector_state(state, crtc);

	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);

	verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);

drivers/gpu/drm/i915/intel_pm.c

+129 −9
Original line number Diff line number Diff line
@@ -4368,7 +4368,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv, 
	skl_ddb_entry_init_from_hw(ddb_y, val);

}



void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,

static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,

				      struct skl_ddb_entry *ddb,

				      struct skl_ddb_entry *ddb_y)

{
@@ -4950,7 +4950,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state) 
	return data_rate;

}



const struct skl_wm_level *

static const struct skl_wm_level *

skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,

		   enum plane_id plane_id,

		   int level)
@@ -4963,7 +4963,7 @@ skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, 
	return &wm->wm[level];

}



const struct skl_wm_level *

static const struct skl_wm_level *

skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,

		   enum plane_id plane_id)

{
@@ -5915,7 +5915,7 @@ void skl_write_cursor_wm(struct intel_plane *plane, 
	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);

}



bool skl_wm_level_equals(const struct skl_wm_level *l1,

static bool skl_wm_level_equals(const struct skl_wm_level *l1,

				const struct skl_wm_level *l2)

{

	return l1->enable == l2->enable &&
@@ -6488,7 +6488,7 @@ static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level) 
	level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);

}



void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,

static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,

				     struct skl_pipe_wm *out)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -7166,6 +7166,126 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv) 
		!(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);

}



void intel_wm_state_verify(struct intel_crtc *crtc,

			   struct intel_crtc_state *new_crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct skl_hw_state {

		struct skl_ddb_entry ddb[I915_MAX_PLANES];

		struct skl_ddb_entry ddb_y[I915_MAX_PLANES];

		struct skl_pipe_wm wm;

	} *hw;

	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;

	int level, max_level = ilk_wm_max_level(dev_priv);

	struct intel_plane *plane;

	u8 hw_enabled_slices;



	if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active)

		return;



	hw = kzalloc(sizeof(*hw), GFP_KERNEL);

	if (!hw)

		return;



	skl_pipe_wm_get_hw_state(crtc, &hw->wm);



	skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);



	hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);



	if (DISPLAY_VER(dev_priv) >= 11 &&

	    hw_enabled_slices != dev_priv->dbuf.enabled_slices)

		drm_err(&dev_priv->drm,

			"mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",

			dev_priv->dbuf.enabled_slices,

			hw_enabled_slices);



	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {

		const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;

		const struct skl_wm_level *hw_wm_level, *sw_wm_level;



		/* Watermarks */

		for (level = 0; level <= max_level; level++) {

			hw_wm_level = &hw->wm.planes[plane->id].wm[level];

			sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);



			if (skl_wm_level_equals(hw_wm_level, sw_wm_level))

				continue;



			drm_err(&dev_priv->drm,

				"[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",

				plane->base.base.id, plane->base.name, level,

				sw_wm_level->enable,

				sw_wm_level->blocks,

				sw_wm_level->lines,

				hw_wm_level->enable,

				hw_wm_level->blocks,

				hw_wm_level->lines);

		}



		hw_wm_level = &hw->wm.planes[plane->id].trans_wm;

		sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);



		if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {

			drm_err(&dev_priv->drm,

				"[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",

				plane->base.base.id, plane->base.name,

				sw_wm_level->enable,

				sw_wm_level->blocks,

				sw_wm_level->lines,

				hw_wm_level->enable,

				hw_wm_level->blocks,

				hw_wm_level->lines);

		}



		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;

		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;



		if (HAS_HW_SAGV_WM(dev_priv) &&

		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {

			drm_err(&dev_priv->drm,

				"[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",

				plane->base.base.id, plane->base.name,

				sw_wm_level->enable,

				sw_wm_level->blocks,

				sw_wm_level->lines,

				hw_wm_level->enable,

				hw_wm_level->blocks,

				hw_wm_level->lines);

		}



		hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;

		sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;



		if (HAS_HW_SAGV_WM(dev_priv) &&

		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {

			drm_err(&dev_priv->drm,

				"[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",

				plane->base.base.id, plane->base.name,

				sw_wm_level->enable,

				sw_wm_level->blocks,

				sw_wm_level->lines,

				hw_wm_level->enable,

				hw_wm_level->blocks,

				hw_wm_level->lines);

		}



		/* DDB */

		hw_ddb_entry = &hw->ddb[PLANE_CURSOR];

		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];



		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {

			drm_err(&dev_priv->drm,

				"[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",

				plane->base.base.id, plane->base.name,

				sw_ddb_entry->start, sw_ddb_entry->end,

				hw_ddb_entry->start, hw_ddb_entry->end);

		}

	}



	kfree(hw);

}



void intel_enable_ipc(struct drm_i915_private *dev_priv)

{

	u32 val;

drivers/gpu/drm/i915/intel_pm.h

+2 −12
Original line number Diff line number Diff line
@@ -35,15 +35,12 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv); 
void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);

void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);

void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);

void intel_wm_state_verify(struct intel_crtc *crtc,

			   struct intel_crtc_state *new_crtc_state);

u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);

void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,

			       struct skl_ddb_entry *ddb_y,

			       struct skl_ddb_entry *ddb_uv);

void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);

u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,

			    const struct skl_ddb_entry *entry);

void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,

			      struct skl_pipe_wm *out);

void g4x_wm_sanitize(struct drm_i915_private *dev_priv);

void vlv_wm_sanitize(struct drm_i915_private *dev_priv);

void skl_wm_sanitize(struct drm_i915_private *dev_priv);
@@ -51,13 +48,6 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv, 
			   const struct intel_bw_state *bw_state);

void intel_sagv_pre_plane_update(struct intel_atomic_state *state);

void intel_sagv_post_plane_update(struct intel_atomic_state *state);

const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,

					      enum plane_id plane_id,

					      int level);

const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,

					      enum plane_id plane_id);

bool skl_wm_level_equals(const struct skl_wm_level *l1,

			 const struct skl_wm_level *l2);

bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,

				 const struct skl_ddb_entry *entries,

				 int num_entries, int ignore_idx);