Commit 88ae6c65 authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/psr: Unify panel replay enable/disable sink 



Unify enabling and disabling of psr/panel replay for a sink. Modify
intel_psr_enable_sink accordingly and use it for both cases.

v3:
  - move psr2_su_region_et_valid to be check for PSR2 only
v2:
  - enable panel replay for sink before link training
  - write ALPM_CONFIG only for PSR
  - add DP_PSR_CRC_VERIFICATION only for PSR
  - take care of disable sink as well

Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-8-jouni.hogander@intel.com
parent 251ff160

drivers/gpu/drm/i915/display/intel_ddi.c

+5 −6
Original line number Diff line number Diff line
@@ -2809,15 +2809,14 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 
				    const struct drm_connector_state *conn_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);



	if (HAS_DP20(dev_priv)) {

	if (HAS_DP20(dev_priv))

		intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),

					    crtc_state);



	/* Panel replay has to be enabled in sink dpcd before link training. */

	if (crtc_state->has_panel_replay)

			drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,

					   DP_PANEL_REPLAY_ENABLE);

	}

		intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state);



	if (DISPLAY_VER(dev_priv) >= 14)

		mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_psr.c

+43 −17
Original line number Diff line number Diff line
@@ -638,39 +638,58 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp) 
	return false;

}



static void intel_psr_enable_sink(struct intel_dp *intel_dp)

static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp *intel_dp)

{

	return intel_dp->psr.panel_replay_enabled ?

		PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG;

}



/*

 * Note: Most of the bits are same in PANEL_REPLAY_CONFIG and DP_PSR_EN_CFG. We

 * are relying on PSR definitions on these "common" bits.

 */

void intel_psr_enable_sink(struct intel_dp *intel_dp,

			   const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	u8 dpcd_val = DP_PSR_ENABLE;



	if (intel_dp->psr.panel_replay_enabled)

		return;



	if (intel_dp->psr.psr2_enabled) {

	if (crtc_state->has_psr2) {

		/* Enable ALPM at sink for psr2 */

		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,

		if (!crtc_state->has_panel_replay) {

			drm_dp_dpcd_writeb(&intel_dp->aux,

					   DP_RECEIVER_ALPM_CONFIG,

					   DP_ALPM_ENABLE |

					   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);



		dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;

			if (psr2_su_region_et_valid(intel_dp))

				dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET;

		}



		dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;

	} else {

		if (intel_dp->psr.link_standby)

			dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;



		if (DISPLAY_VER(dev_priv) >= 8)

		if (!crtc_state->has_panel_replay && DISPLAY_VER(dev_priv) >= 8)

			dpcd_val |= DP_PSR_CRC_VERIFICATION;

	}



	if (intel_dp->psr.req_psr2_sdp_prior_scanline)

	if (crtc_state->has_panel_replay)

		dpcd_val |= DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |

			DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN;



	if (crtc_state->req_psr2_sdp_prior_scanline)

		dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;



	if (intel_dp->psr.entry_setup_frames > 0)

		dpcd_val |= DP_PSR_FRAME_CAPTURE;



	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);

	drm_dp_dpcd_writeb(&intel_dp->aux,

			   intel_psr_get_enable_sink_offset(intel_dp),

			   dpcd_val);



	if (intel_dp_is_edp(intel_dp))

		drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);

}
@@ -1955,12 +1974,17 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, 
	} else {

		drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",

			    intel_dp->psr.psr2_enabled ? "2" : "1");



		/*

		 * Panel replay has to be enabled before link training: doing it

		 * only for PSR here.

		 */

		intel_psr_enable_sink(intel_dp, crtc_state);

	}



	if (intel_dp_is_edp(intel_dp))

		intel_snps_phy_update_psr_power_state(&dig_port->base, true);



	intel_psr_enable_sink(intel_dp);

	intel_psr_enable_source(intel_dp, crtc_state);

	intel_dp->psr.enabled = true;

	intel_dp->psr.paused = false;
@@ -2078,9 +2102,11 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) 
	}



	/* Disable PSR on Sink */

	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);

	drm_dp_dpcd_writeb(&intel_dp->aux,

			   intel_psr_get_enable_sink_offset(intel_dp), 0);



	if (intel_dp->psr.psr2_enabled)

	if (!intel_dp->psr.panel_replay_enabled &&

	    intel_dp->psr.psr2_enabled)

		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);



	intel_dp->psr.enabled = false;

drivers/gpu/drm/i915/display/intel_psr.h

+2 −0
Original line number Diff line number Diff line
@@ -23,6 +23,8 @@ struct intel_plane_state; 


bool intel_encoder_can_psr(struct intel_encoder *encoder);

void intel_psr_init_dpcd(struct intel_dp *intel_dp);

void intel_psr_enable_sink(struct intel_dp *intel_dp,

			   const struct intel_crtc_state *crtc_state);

void intel_psr_pre_plane_update(struct intel_atomic_state *state,

				struct intel_crtc *crtc);

void intel_psr_post_plane_update(struct intel_atomic_state *state,