Unverified Commit 897117e3 authored by Yao Zi's avatar Yao Zi Committed by Stephen Boyd
Browse files

clk: loongson2: Support scale clocks with an alternative mode 



LS2K0300 and LS2K1500 ship scale clocks with an alternative mode.
There's one mode bit in clock configuration register indicating the
operation mode.

When mode bit is unset, the scale clock acts the same as previous
generation of scale clocks. When it's set, a different equation for
calculating result frequency, Fout = Fin / (scale + 1), is used.

This patch adds frequency calculation support for the scale clock
variant. A helper macro, CLK_SCALE_MODE, is added to simplify
definitions.

Signed-off-by: default avatarYao Zi <ziyao@disroot.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 499f8184

drivers/clk/clk-loongson2.c

+23 −3
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ struct loongson2_clk_data { 
	u8 div_width;

	u8 mult_shift;

	u8 mult_width;

	u8 bit_idx;

};



struct loongson2_clk_board_info {
@@ -96,6 +97,19 @@ struct loongson2_clk_board_info { 
		.div_width	= _dwidth,			\

	}



#define CLK_SCALE_MODE(_id, _name, _pname, _offset,		\

		  _dshift, _dwidth, _midx)			\

	{							\

		.id		= _id,				\

		.type		= CLK_TYPE_SCALE,		\

		.name		= _name,			\

		.parent_name	= _pname,			\

		.reg_offset	= _offset,			\

		.div_shift	= _dshift,			\

		.div_width	= _dwidth,			\

		.bit_idx	= _midx + 1,			\

	}



#define CLK_GATE(_id, _name, _pname, _offset, _bidx)		\

	{							\

		.id		= _id,				\
@@ -243,13 +257,18 @@ static const struct clk_ops loongson2_pll_recalc_ops = { 
static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw,

						     unsigned long parent_rate)

{

	u64 val, mult;

	u64 val, scale;

	u32 mode = 0;

	struct loongson2_clk_data *clk = to_loongson2_clk(hw);



	val  = readq(clk->reg);

	mult = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;

	scale = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;



	if (clk->bit_idx)

		mode = val & BIT(clk->bit_idx - 1);



	return div_u64((u64)parent_rate * mult, 8);

	return mode == 0 ? div_u64((u64)parent_rate * scale, 8) :

			   div_u64((u64)parent_rate, scale);

}



static const struct clk_ops loongson2_freqscale_recalc_ops = {
@@ -284,6 +303,7 @@ static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider *clp, 
	clk->div_width	= cld->div_width;

	clk->mult_shift	= cld->mult_shift;

	clk->mult_width	= cld->mult_width;

	clk->bit_idx	= cld->bit_idx;

	clk->hw.init	= &init;



	hw = &clk->hw;