Unverified Commit 89b37e49 authored by Mark Brown's avatar Mark Brown
Browse files

spi-nand/spi-mem DTR support 

Merge series from Miquel Raynal <miquel.raynal@bootlin.com>:

Here is a (big) series supposed to bring DTR support in SPI-NAND.
parents 5e56618e f0006897

drivers/mtd/nand/spi/core.c

+2 −0
Original line number Diff line number Diff line
@@ -1214,6 +1214,8 @@ spinand_select_op_variant(struct spinand_device *spinand, 
			if (ret)

				break;



			spi_mem_adjust_op_freq(spinand->spimem, &op);



			if (!spi_mem_supports_op(spinand->spimem, &op))

				break;

drivers/spi/spi-amd.c

+11 −10
Original line number Diff line number Diff line
@@ -298,19 +298,16 @@ static const struct amd_spi_freq amd_spi_freq[] = { 
	{ AMD_SPI_MIN_HZ,   F_800KHz,         0},

};



static int amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz)

static void amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz)

{

	unsigned int i, spd7_val, alt_spd;



	if (speed_hz < AMD_SPI_MIN_HZ)

		return -EINVAL;



	for (i = 0; i < ARRAY_SIZE(amd_spi_freq); i++)

		if (speed_hz >= amd_spi_freq[i].speed_hz)

			break;



	if (amd_spi->speed_hz == amd_spi_freq[i].speed_hz)

		return 0;

		return;



	amd_spi->speed_hz = amd_spi_freq[i].speed_hz;
@@ -329,8 +326,6 @@ static int amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz) 
		amd_spi_setclear_reg32(amd_spi, AMD_SPI_SPEED_REG, spd7_val,

				       AMD_SPI_SPD7_MASK);

	}



	return 0;

}



static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
@@ -479,6 +474,9 @@ static bool amd_spi_supports_op(struct spi_mem *mem, 
		return false;

	}



	if (op->max_freq < mem->spi->controller->min_speed_hz)

		return false;



	return spi_mem_default_supports_op(mem, op);

}
@@ -676,9 +674,7 @@ static int amd_spi_exec_mem_op(struct spi_mem *mem, 


	amd_spi = spi_controller_get_devdata(mem->spi->controller);



	ret = amd_set_spi_freq(amd_spi, mem->spi->max_speed_hz);

	if (ret)

		return ret;

	amd_set_spi_freq(amd_spi, op->max_freq);



	if (amd_spi->version == AMD_SPI_V2)

		amd_set_spi_addr_mode(amd_spi, op);
@@ -705,6 +701,10 @@ static const struct spi_controller_mem_ops amd_spi_mem_ops = { 
	.supports_op = amd_spi_supports_op,

};



static const struct spi_controller_mem_caps amd_spi_mem_caps = {

	.per_op_freq = true,

};



static int amd_spi_host_transfer(struct spi_controller *host,

				   struct spi_message *msg)

{
@@ -782,6 +782,7 @@ static int amd_spi_probe(struct platform_device *pdev) 
	host->setup = amd_spi_host_setup;

	host->transfer_one_message = amd_spi_host_transfer;

	host->mem_ops = &amd_spi_mem_ops;

	host->mem_caps = &amd_spi_mem_caps;

	host->max_transfer_size = amd_spi_max_transfer_size;

	host->max_message_size = amd_spi_max_transfer_size;

drivers/spi/spi-amlogic-spifc-a1.c

+6 −1
Original line number Diff line number Diff line
@@ -259,7 +259,7 @@ static int amlogic_spifc_a1_exec_op(struct spi_mem *mem, 
	size_t data_size = op->data.nbytes;

	int ret;



	ret = amlogic_spifc_a1_set_freq(spifc, mem->spi->max_speed_hz);

	ret = amlogic_spifc_a1_set_freq(spifc, op->max_freq);

	if (ret)

		return ret;
@@ -320,6 +320,10 @@ static const struct spi_controller_mem_ops amlogic_spifc_a1_mem_ops = { 
	.adjust_op_size = amlogic_spifc_a1_adjust_op_size,

};



static const struct spi_controller_mem_caps amlogic_spifc_a1_mem_caps = {

	.per_op_freq = true,

};



static int amlogic_spifc_a1_probe(struct platform_device *pdev)

{

	struct spi_controller *ctrl;
@@ -356,6 +360,7 @@ static int amlogic_spifc_a1_probe(struct platform_device *pdev) 
	ctrl->bits_per_word_mask = SPI_BPW_MASK(8);

	ctrl->auto_runtime_pm = true;

	ctrl->mem_ops = &amlogic_spifc_a1_mem_ops;

	ctrl->mem_caps = &amlogic_spifc_a1_mem_caps;

	ctrl->min_speed_hz = SPIFC_A1_MIN_HZ;

	ctrl->max_speed_hz = SPIFC_A1_MAX_HZ;

	ctrl->mode_bits = (SPI_RX_DUAL | SPI_TX_DUAL |

drivers/spi/spi-cadence-quadspi.c

+2 −1
Original line number Diff line number Diff line
@@ -1433,7 +1433,7 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 
	struct cqspi_flash_pdata *f_pdata;



	f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)];

	cqspi_configure(f_pdata, mem->spi->max_speed_hz);

	cqspi_configure(f_pdata, op->max_freq);



	if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {

	/*
@@ -1682,6 +1682,7 @@ static const struct spi_controller_mem_ops cqspi_mem_ops = { 


static const struct spi_controller_mem_caps cqspi_mem_caps = {

	.dtr = true,

	.per_op_freq = true,

};



static int cqspi_setup_flash(struct cqspi_st *cqspi)

drivers/spi/spi-dw-core.c

+8 −2
Original line number Diff line number Diff line
@@ -677,7 +677,7 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 
	 * operation. Transmit-only mode is suitable for the rest of them.

	 */

	cfg.dfs = 8;

	cfg.freq = clamp(mem->spi->max_speed_hz, 0U, dws->max_mem_freq);

	cfg.freq = clamp(op->max_freq, 0U, dws->max_mem_freq);

	if (op->data.dir == SPI_MEM_DATA_IN) {

		cfg.tmode = DW_SPI_CTRLR0_TMOD_EPROMREAD;

		cfg.ndf = op->data.nbytes;
@@ -894,6 +894,10 @@ static void dw_spi_hw_init(struct device *dev, struct dw_spi *dws) 
		dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);

}



static const struct spi_controller_mem_caps dw_spi_mem_caps = {

	.per_op_freq = true,

};



int dw_spi_add_host(struct device *dev, struct dw_spi *dws)

{

	struct spi_controller *host;
@@ -941,8 +945,10 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) 
		host->set_cs = dw_spi_set_cs;

	host->transfer_one = dw_spi_transfer_one;

	host->handle_err = dw_spi_handle_err;

	if (dws->mem_ops.exec_op)

	if (dws->mem_ops.exec_op) {

		host->mem_ops = &dws->mem_ops;

		host->mem_caps = &dw_spi_mem_caps;

	}

	host->max_speed_hz = dws->max_freq;

	host->flags = SPI_CONTROLLER_GPIO_SS;

	host->auto_runtime_pm = true;