Commit 8a37cd4d authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/pps: convert intel_pps.[ch] to struct intel_display 



Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_pps.[ch] to struct intel_display.

Some stragglers are left behind where needed.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/bea51b0d9e4546ba21d0d4eb01ca1097fda095ab.1725012870.git.jani.nikula@intel.com
parent 631ef2e6

drivers/gpu/drm/i915/display/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -7793,7 +7793,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv) 
	struct intel_encoder *encoder;

	bool dpd_is_edp = false;



	intel_pps_unlock_regs_wa(dev_priv);

	intel_pps_unlock_regs_wa(display);



	if (!HAS_DISPLAY(dev_priv))

		return;

drivers/gpu/drm/i915/display/intel_display_driver.c

+1 −1
Original line number Diff line number Diff line
@@ -428,7 +428,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915) 


	intel_panel_sanitize_ssc(i915);



	intel_pps_setup(i915);

	intel_pps_setup(display);



	intel_gmbus_setup(i915);

drivers/gpu/drm/i915/display/intel_display_power_well.c

+11 −4
Original line number Diff line number Diff line
@@ -861,6 +861,8 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv) 


void bxt_enable_dc9(struct drm_i915_private *dev_priv)

{

	struct intel_display *display = &dev_priv->display;



	assert_can_enable_dc9(dev_priv);



	drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
@@ -870,19 +872,21 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv) 
	 * because PPS registers are always on.

	 */

	if (!HAS_PCH_SPLIT(dev_priv))

		intel_pps_reset_all(dev_priv);

		intel_pps_reset_all(display);

	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);

}



void bxt_disable_dc9(struct drm_i915_private *dev_priv)

{

	struct intel_display *display = &dev_priv->display;



	assert_can_disable_dc9(dev_priv);



	drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n");



	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);



	intel_pps_unlock_regs_wa(dev_priv);

	intel_pps_unlock_regs_wa(display);

}



static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
@@ -1184,6 +1188,7 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 


static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)

{

	struct intel_display *display = &dev_priv->display;

	struct intel_encoder *encoder;

	enum pipe pipe;
@@ -1229,11 +1234,13 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 


	intel_vga_redisable_power_on(dev_priv);



	intel_pps_unlock_regs_wa(dev_priv);

	intel_pps_unlock_regs_wa(display);

}



static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)

{

	struct intel_display *display = &dev_priv->display;



	spin_lock_irq(&dev_priv->irq_lock);

	valleyview_disable_display_irqs(dev_priv);

	spin_unlock_irq(&dev_priv->irq_lock);
@@ -1241,7 +1248,7 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 
	/* make sure we're done processing display irqs */

	intel_synchronize_irq(dev_priv);



	intel_pps_reset_all(dev_priv);

	intel_pps_reset_all(display);



	/* Prevent us from re-enabling polling on accident in late suspend */

	if (!dev_priv->drm.dev->power.is_suspended)

drivers/gpu/drm/i915/display/intel_display_reset.c

+4 −3
Original line number Diff line number Diff line
@@ -83,7 +83,8 @@ void intel_display_reset_prepare(struct drm_i915_private *dev_priv) 


void intel_display_reset_finish(struct drm_i915_private *i915)

{

	struct drm_modeset_acquire_ctx *ctx = &i915->display.restore.reset_ctx;

	struct intel_display *display = &i915->display;

	struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx;

	struct drm_atomic_state *state;

	int ret;
@@ -94,7 +95,7 @@ void intel_display_reset_finish(struct drm_i915_private *i915) 
	if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags))

		return;



	state = fetch_and_zero(&i915->display.restore.modeset_state);

	state = fetch_and_zero(&display->restore.modeset_state);

	if (!state)

		goto unlock;
@@ -112,7 +113,7 @@ void intel_display_reset_finish(struct drm_i915_private *i915) 
		 * The display has been reset as well,

		 * so need a full re-initialization.

		 */

		intel_pps_unlock_regs_wa(i915);

		intel_pps_unlock_regs_wa(display);

		intel_display_driver_init_hw(i915);

		intel_clock_gating_init(i915);

		intel_hpd_init(i915);

drivers/gpu/drm/i915/display/intel_dpll.c

+6 −3
Original line number Diff line number Diff line
@@ -1823,6 +1823,7 @@ static bool i9xx_has_pps(struct drm_i915_private *dev_priv) 


void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
@@ -1833,7 +1834,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) 


	/* PLL is protected by panel, make sure we can write it */

	if (i9xx_has_pps(dev_priv))

		assert_pps_unlocked(dev_priv, pipe);

		assert_pps_unlocked(display, pipe);



	intel_de_write(dev_priv, FP0(pipe), hw_state->fp0);

	intel_de_write(dev_priv, FP1(pipe), hw_state->fp1);
@@ -2004,6 +2005,7 @@ static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) 


void vlv_enable_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
@@ -2012,7 +2014,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state) 
	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);



	/* PLL is protected by panel, make sure we can write it */

	assert_pps_unlocked(dev_priv, pipe);

	assert_pps_unlocked(display, pipe);



	/* Enable Refclk */

	intel_de_write(dev_priv, DPLL(dev_priv, pipe),
@@ -2150,6 +2152,7 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) 


void chv_enable_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
@@ -2158,7 +2161,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) 
	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);



	/* PLL is protected by panel, make sure we can write it */

	assert_pps_unlocked(dev_priv, pipe);

	assert_pps_unlocked(display, pipe);



	/* Enable Refclk and SSC */

	intel_de_write(dev_priv, DPLL(dev_priv, pipe),