Commit 8aaeb253 authored by Meenakshikumar Somasundaram's avatar Meenakshikumar Somasundaram Committed by Alex Deucher
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drm/amd/display: Fix pixel rate divider policy for 1 pixel per cycle config 



[Why]
Pixel rate dividor was not programmed correctly for 1 pixel per cycle
configuration for empty tu case.

[How]
Included check for empty tu when pixel rate dividor values were selected.

Reviewed-by: default avatarMichael Strauss <michael.strauss@amd.com>
Signed-off-by: default avatarMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: default avatarZaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: default avatarMark Broadworth <mark.broadworth@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8f772d79

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

+3 −1
Original line number Diff line number Diff line
@@ -1181,6 +1181,7 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign 
	struct dc_stream_state *stream = pipe_ctx->stream;

	unsigned int odm_combine_factor = 0;

	bool two_pix_per_container = false;

	struct dce_hwseq *hws = stream->ctx->dc->hwseq;



	two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

	odm_combine_factor = get_odm_config(pipe_ctx, NULL);
@@ -1201,7 +1202,8 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign 
		} else {

			*k1_div = PIXEL_RATE_DIV_BY_1;

			*k2_div = PIXEL_RATE_DIV_BY_4;

			if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))

			if ((odm_combine_factor == 2) || (hws->funcs.is_dp_dig_pixel_rate_div_policy &&

				hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)))

				*k2_div = PIXEL_RATE_DIV_BY_2;

		}

	}

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

+1 −1
Original line number Diff line number Diff line
@@ -158,7 +158,7 @@ static const struct hwseq_private_funcs dcn351_private_funcs = { 
	.set_mcm_luts = dcn32_set_mcm_luts,

	.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,

	.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,

	.is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,

	.is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy,

	.dsc_pg_control = dcn35_dsc_pg_control,

	.dsc_pg_status = dcn32_dsc_pg_status,

	.enable_plane = dcn35_enable_plane,