Commit 8ac6067b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-sev-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 SEV updates from Ingo Molnar:

 - Improve sme_enable() PIC build robustness (Kevin Loughlin)

 - Simplify vc_handle_msr() a bit (Peng Hao)

[ Just reminding myself and everybody else about the endless stream of
  x86 TLAs: "SEV" is AMD's Secure Encrypted Virtualization  - Linus ]

* tag 'x86-sev-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/sev: Simplify the code by removing unnecessary 'else' statement
  x86/sev: Add missing RIP_REL_REF() invocations during sme_enable()
parents a49a879f f0373cc0

arch/x86/coco/sev/core.c

+1 −2
Original line number Diff line number Diff line
@@ -1480,7 +1480,6 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) 
	case MSR_AMD64_GUEST_TSC_FREQ:

		if (sev_status & MSR_AMD64_SNP_SECURE_TSC)

			return __vc_handle_secure_tsc_msrs(regs, write);

		else

		break;

	default:

		break;

arch/x86/mm/mem_encrypt_identity.c

+2 −2
Original line number Diff line number Diff line
@@ -563,7 +563,7 @@ void __head sme_enable(struct boot_params *bp) 
	}



	RIP_REL_REF(sme_me_mask) = me_mask;

	physical_mask &= ~me_mask;

	cc_vendor = CC_VENDOR_AMD;

	RIP_REL_REF(physical_mask) &= ~me_mask;

	RIP_REL_REF(cc_vendor) = CC_VENDOR_AMD;

	cc_set_mask(me_mask);

}