Commit 8ae4be56 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2022-08-11' of... 

Merge tag 'drm-intel-next-fixes-2022-08-11' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- disable pci resize on 32-bit systems (Nirmoy)
- don't leak the ccs state (Matt)
- TLB invalidation fixes (Chris)
[now with all fixes of fixes]

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YvVumNCga+90fYN0@intel.com
parents 568035b0 9d50bff4

drivers/gpu/drm/i915/gem/i915_gem_object.c

+4 −12
Original line number Diff line number Diff line
@@ -268,7 +268,7 @@ static void __i915_gem_object_free_mmaps(struct drm_i915_gem_object *obj) 
 */

void __i915_gem_object_pages_fini(struct drm_i915_gem_object *obj)

{

	assert_object_held(obj);

	assert_object_held_shared(obj);



	if (!list_empty(&obj->vma.list)) {

		struct i915_vma *vma;
@@ -331,15 +331,7 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915, 
			continue;

		}



		if (!i915_gem_object_trylock(obj, NULL)) {

			/* busy, toss it back to the pile */

			if (llist_add(&obj->freed, &i915->mm.free_list))

				queue_delayed_work(i915->wq, &i915->mm.free_work, msecs_to_jiffies(10));

			continue;

		}



		__i915_gem_object_pages_fini(obj);

		i915_gem_object_unlock(obj);

		__i915_gem_free_object(obj);



		/* But keep the pointer alive for RCU-protected lookups */
@@ -359,7 +351,7 @@ void i915_gem_flush_free_objects(struct drm_i915_private *i915) 
static void __i915_gem_free_work(struct work_struct *work)

{

	struct drm_i915_private *i915 =

		container_of(work, struct drm_i915_private, mm.free_work.work);

		container_of(work, struct drm_i915_private, mm.free_work);



	i915_gem_flush_free_objects(i915);

}
@@ -391,7 +383,7 @@ static void i915_gem_free_object(struct drm_gem_object *gem_obj) 
	 */



	if (llist_add(&obj->freed, &i915->mm.free_list))

		queue_delayed_work(i915->wq, &i915->mm.free_work, 0);

		queue_work(i915->wq, &i915->mm.free_work);

}



void __i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
@@ -745,7 +737,7 @@ bool i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj) 


void i915_gem_init__objects(struct drm_i915_private *i915)

{

	INIT_DELAYED_WORK(&i915->mm.free_work, __i915_gem_free_work);

	INIT_WORK(&i915->mm.free_work, __i915_gem_free_work);

}



void i915_objects_module_exit(void)

drivers/gpu/drm/i915/gem/i915_gem_object_types.h

+2 −1
Original line number Diff line number Diff line
@@ -335,7 +335,6 @@ struct drm_i915_gem_object { 
#define I915_BO_READONLY          BIT(7)

#define I915_TILING_QUIRK_BIT     8 /* unknown swizzling; do not release! */

#define I915_BO_PROTECTED         BIT(9)

#define I915_BO_WAS_BOUND_BIT     10

	/**

	 * @mem_flags - Mutable placement-related flags

	 *
@@ -616,6 +615,8 @@ struct drm_i915_gem_object { 
		 * pages were last acquired.

		 */

		bool dirty:1;



		u32 tlb;

	} mm;



	struct {

drivers/gpu/drm/i915/gem/i915_gem_pages.c

+16 −9
Original line number Diff line number Diff line
@@ -6,14 +6,15 @@ 


#include <drm/drm_cache.h>



#include "gt/intel_gt.h"

#include "gt/intel_gt_pm.h"



#include "i915_drv.h"

#include "i915_gem_object.h"

#include "i915_scatterlist.h"

#include "i915_gem_lmem.h"

#include "i915_gem_mman.h"



#include "gt/intel_gt.h"



void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,

				 struct sg_table *pages,

				 unsigned int sg_page_sizes)
@@ -190,6 +191,18 @@ static void unmap_object(struct drm_i915_gem_object *obj, void *ptr) 
		vunmap(ptr);

}



static void flush_tlb_invalidate(struct drm_i915_gem_object *obj)

{

	struct drm_i915_private *i915 = to_i915(obj->base.dev);

	struct intel_gt *gt = to_gt(i915);



	if (!obj->mm.tlb)

		return;



	intel_gt_invalidate_tlb(gt, obj->mm.tlb);

	obj->mm.tlb = 0;

}



struct sg_table *

__i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)

{
@@ -215,13 +228,7 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj) 
	__i915_gem_object_reset_page_iter(obj);

	obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0;



	if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {

		struct drm_i915_private *i915 = to_i915(obj->base.dev);

		intel_wakeref_t wakeref;



		with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref)

			intel_gt_invalidate_tlbs(to_gt(i915));

	}

	flush_tlb_invalidate(obj);



	return pages;

}

drivers/gpu/drm/i915/gt/intel_gt.c

+60 −17
Original line number Diff line number Diff line
@@ -11,7 +11,9 @@ 
#include "pxp/intel_pxp.h"



#include "i915_drv.h"

#include "i915_perf_oa_regs.h"

#include "intel_context.h"

#include "intel_engine_pm.h"

#include "intel_engine_regs.h"

#include "intel_ggtt_gmch.h"

#include "intel_gt.h"
@@ -36,8 +38,6 @@ static void __intel_gt_init_early(struct intel_gt *gt) 
{

	spin_lock_init(&gt->irq_lock);



	mutex_init(&gt->tlb_invalidate_lock);



	INIT_LIST_HEAD(&gt->closed_vma);

	spin_lock_init(&gt->closed_lock);
@@ -48,6 +48,8 @@ static void __intel_gt_init_early(struct intel_gt *gt) 
	intel_gt_init_reset(gt);

	intel_gt_init_requests(gt);

	intel_gt_init_timelines(gt);

	mutex_init(&gt->tlb.invalidate_lock);

	seqcount_mutex_init(&gt->tlb.seqno, &gt->tlb.invalidate_lock);

	intel_gt_pm_init_early(gt);



	intel_uc_init_early(&gt->uc);
@@ -768,6 +770,7 @@ void intel_gt_driver_late_release_all(struct drm_i915_private *i915) 
		intel_gt_fini_requests(gt);

		intel_gt_fini_reset(gt);

		intel_gt_fini_timelines(gt);

		mutex_destroy(&gt->tlb.invalidate_lock);

		intel_engines_free(gt);

	}

}
@@ -906,7 +909,7 @@ get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, 
	return rb;

}



void intel_gt_invalidate_tlbs(struct intel_gt *gt)

static void mmio_invalidate_full(struct intel_gt *gt)

{

	static const i915_reg_t gen8_regs[] = {

		[RENDER_CLASS]			= GEN8_RTCR,
@@ -924,13 +927,11 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) 
	struct drm_i915_private *i915 = gt->i915;

	struct intel_uncore *uncore = gt->uncore;

	struct intel_engine_cs *engine;

	intel_engine_mask_t awake, tmp;

	enum intel_engine_id id;

	const i915_reg_t *regs;

	unsigned int num = 0;



	if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))

		return;



	if (GRAPHICS_VER(i915) == 12) {

		regs = gen12_regs;

		num = ARRAY_SIZE(gen12_regs);
@@ -945,28 +946,41 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) 
			  "Platform does not implement TLB invalidation!"))

		return;



	GEM_TRACE("\n");



	assert_rpm_wakelock_held(&i915->runtime_pm);



	mutex_lock(&gt->tlb_invalidate_lock);

	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);



	spin_lock_irq(&uncore->lock); /* serialise invalidate with GT reset */



	awake = 0;

	for_each_engine(engine, gt, id) {

		struct reg_and_bit rb;



		if (!intel_engine_pm_is_awake(engine))

			continue;



		rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);

		if (!i915_mmio_reg_offset(rb.reg))

			continue;



		intel_uncore_write_fw(uncore, rb.reg, rb.bit);

		awake |= engine->mask;

	}



	GT_TRACE(gt, "invalidated engines %08x\n", awake);



	/* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */

	if (awake &&

	    (IS_TIGERLAKE(i915) ||

	     IS_DG1(i915) ||

	     IS_ROCKETLAKE(i915) ||

	     IS_ALDERLAKE_S(i915) ||

	     IS_ALDERLAKE_P(i915)))

		intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1);



	spin_unlock_irq(&uncore->lock);



	for_each_engine(engine, gt, id) {

	for_each_engine_masked(engine, gt, awake, tmp) {

		struct reg_and_bit rb;



		/*

		 * HW architecture suggest typical invalidation time at 40us,

		 * with pessimistic cases up to 100us and a recommendation to
@@ -974,12 +988,8 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) 
		 */

		const unsigned int timeout_us = 100;

		const unsigned int timeout_ms = 4;

		struct reg_and_bit rb;



		rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);

		if (!i915_mmio_reg_offset(rb.reg))

			continue;



		if (__intel_wait_for_register_fw(uncore,

						 rb.reg, rb.bit, 0,

						 timeout_us, timeout_ms,
@@ -996,5 +1006,38 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) 
	 * transitions.

	 */

	intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL);

	mutex_unlock(&gt->tlb_invalidate_lock);

}



static bool tlb_seqno_passed(const struct intel_gt *gt, u32 seqno)

{

	u32 cur = intel_gt_tlb_seqno(gt);



	/* Only skip if a *full* TLB invalidate barrier has passed */

	return (s32)(cur - ALIGN(seqno, 2)) > 0;

}



void intel_gt_invalidate_tlb(struct intel_gt *gt, u32 seqno)

{

	intel_wakeref_t wakeref;



	if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))

		return;



	if (intel_gt_is_wedged(gt))

		return;



	if (tlb_seqno_passed(gt, seqno))

		return;



	with_intel_gt_pm_if_awake(gt, wakeref) {

		mutex_lock(&gt->tlb.invalidate_lock);

		if (tlb_seqno_passed(gt, seqno))

			goto unlock;



		mmio_invalidate_full(gt);



		write_seqcount_invalidate(&gt->tlb.seqno);

unlock:

		mutex_unlock(&gt->tlb.invalidate_lock);

	}

}

drivers/gpu/drm/i915/gt/intel_gt.h

+11 −1
Original line number Diff line number Diff line
@@ -101,6 +101,16 @@ void intel_gt_info_print(const struct intel_gt_info *info, 


void intel_gt_watchdog_work(struct work_struct *work);



void intel_gt_invalidate_tlbs(struct intel_gt *gt);

static inline u32 intel_gt_tlb_seqno(const struct intel_gt *gt)

{

	return seqprop_sequence(&gt->tlb.seqno);

}



static inline u32 intel_gt_next_invalidate_tlb_full(const struct intel_gt *gt)

{

	return intel_gt_tlb_seqno(gt) | 1;

}



void intel_gt_invalidate_tlb(struct intel_gt *gt, u32 seqno);



#endif /* __INTEL_GT_H__ */