Commit 8bc7cb73 authored by Patrick Wildt's avatar Patrick Wildt Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: x1e80100-yoga: add wifi calibration variant



Describe the bus topology for PCIe domain 4 and add the ath12k
calibration variant so that the board file (calibration data) can be
loaded.

Signed-off-by: default avatarPatrick Wildt <patrick@blueri.se>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/ZpV7OeGNIGGpqNC0@windev.fritz.box


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 8400291e
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+9 −0
Original line number Diff line number Diff line
@@ -635,6 +635,15 @@ &pcie4_phy {
	status = "okay";
};

&pcie4_port0 {
	wifi@0 {
		compatible = "pci17cb,1107";
		reg = <0x10000 0x0 0x0 0x0 0x0>;

		qcom,ath12k-calibration-variant = "LES790";
	};
};

&pcie6a {
	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+10 −0
Original line number Diff line number Diff line
@@ -3085,6 +3085,16 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
			phy-names = "pciephy";

			status = "disabled";

			pcie4_port0: pcie@0 {
				device_type = "pci";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				bus-range = <0x01 0xff>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges;
			};
		};

		pcie4_phy: phy@1c0e000 {