Commit 8c4caab0 authored by Khairul Anuar Romli's avatar Khairul Anuar Romli Committed by Dinh Nguyen
Browse files

arm64: dts: socfpga: agilex5: Add dma-coherent property 



Add the `dma-coherent` property to these device nodes to inform the
kernel and DMA subsystem that the devices support hardware-managed
cache coherence.

Changes:
 - Add `dma-coherent` to `cdns,hp-nfc`
 - Add `dma-coherent` to both `snps,axi-dma-1.01a` instances
   (dmac0, dmac1)

This aligns the Agilex5 device tree with the coherent DMA-capable
devices accordingly.

Signed-off-by: default avatarKhairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 8f0b4cce

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -312,6 +312,7 @@ nand: nand-controller@10b80000 { 
			clock-names = "nf_clk";

			cdns,board-delay-ps = <4830>;

			iommus = <&smmu 4>;

			dma-coherent;

			status = "disabled";

		};
@@ -339,6 +340,7 @@ dmac0: dma-controller@10db0000 { 
			snps,priority = <0 1 2 3>;

			snps,axi-max-burst-len = <8>;

			iommus = <&smmu 8>;

			dma-coherent;

		};



		dmac1: dma-controller@10dc0000 {
@@ -357,6 +359,7 @@ dmac1: dma-controller@10dc0000 { 
			snps,priority = <0 1 2 3>;

			snps,axi-max-burst-len = <8>;

			iommus = <&smmu 9>;

			dma-coherent;

		};



		rst: rstmgr@10d11000 {