Commit 8c5fe7d8 authored by Aradhya Bhatia's avatar Aradhya Bhatia Committed by Lucas De Marchi
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drm/xe: Add Wa_16021333562 and Wa_14016712196



Wa_16021333562 and Wa_14016712196 are permanent workarounds that apply
to multiple platforms. Wa_16021333562 applies to platforms ranging from
TGL (12.00) to Xe_LPM (13.00), while Wa_14016712196 from DG2 (12.55) to
Xe_LPG (12.74).

Reviewed-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: default avatarAradhya Bhatia <aradhya.bhatia@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250220094645.358647-2-aradhya.bhatia@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 278d4f42
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+1 −1
Original line number Diff line number Diff line
@@ -342,7 +342,7 @@ static void guc_waklv_init(struct xe_guc_ads *ads)
	offset = guc_ads_waklv_offset(ads);
	remain = guc_ads_waklv_size(ads);

	if (XE_WA(gt, 14019882105))
	if (XE_WA(gt, 14019882105) || XE_WA(gt, 16021333562))
		guc_waklv_enable_simple(ads,
					GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED,
					&offset, &remain);
+4 −0
Original line number Diff line number Diff line
@@ -177,6 +177,10 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
	bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
	u32 flags;

	if (XE_WA(gt, 14016712196))
		i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_DEPTH_CACHE_FLUSH,
				      LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR, 0);

	flags = (PIPE_CONTROL_CS_STALL |
		 PIPE_CONTROL_TILE_CACHE_FLUSH |
		 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+4 −0
Original line number Diff line number Diff line
@@ -43,3 +43,7 @@
no_media_l3	MEDIA_VERSION(3000)
14022866841	GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)
		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0)
16021333562	GRAPHICS_VERSION_RANGE(1200, 1274)
		MEDIA_VERSION(1300)
14016712196	GRAPHICS_VERSION(1255)
		GRAPHICS_VERSION_RANGE(1270, 1274)