Commit 8d7330b3 authored by Lucas Stach's avatar Lucas Stach Committed by David S. Miller
Browse files

net: dsa: microchip: lan9371/2: add 100BaseTX PHY support



On the LAN9371 and LAN9372, the 4th internal PHY is a 100BaseTX PHY
instead of a 100BaseT1 PHY. The 100BaseTX PHYs have a different base
register offset.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarOleksij Rempel <o.rempel@pengutronix.de>
Acked-by: default avatarArun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent df18948d
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+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@
/* all KSZ switches count ports from 1 */
#define KSZ_PORT_1 0
#define KSZ_PORT_2 1
#define KSZ_PORT_4 3

struct ksz_device;
struct ksz_port;
+4 −0
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@@ -55,6 +55,10 @@ static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg)
	u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE;
	u16 temp;

	if ((dev->info->chip_id == LAN9371_CHIP_ID ||
	     dev->info->chip_id == LAN9372_CHIP_ID) && addr == KSZ_PORT_4)
		addr_base = REG_PORT_TX_PHY_CTRL_BASE;

	/* get register address based on the logical port */
	temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2)));

+1 −0
Original line number Diff line number Diff line
@@ -147,6 +147,7 @@

/* 1 - Phy */
#define REG_PORT_T1_PHY_CTRL_BASE	0x0100
#define REG_PORT_TX_PHY_CTRL_BASE	0x0280

/* 3 - xMII */
#define PORT_SGMII_SEL			BIT(7)