Unverified Commit 8ea304cf authored by Ryan Chen's avatar Ryan Chen Committed by Stephen Boyd
Browse files

dt-bindings: clock: ast2700: modify soc0/1 clock define 



-add SOC0_CLK_AHBMUX:
add SOC0_CLK_AHBMUX for ahb clock source divide.
mpll->
      ahb_mux -> div_table -> clk_ahb
hpll->

-new add clock:
 SOC0_CLK_MPHYSRC: UFS MPHY clock source.
 SOC0_CLK_U2PHY_REFCLKSRC: USB2.0 phy clock reference source.
 SOC1_CLK_I3C: I3C clock source.

Signed-off-by: default avatarRyan Chen <ryan_chen@aspeedtech.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 8f5ae30d

include/dt-bindings/clock/aspeed,ast2700-scu.h

+4 −0
Original line number Diff line number Diff line
@@ -68,6 +68,9 @@ 
#define SCU0_CLK_GATE_UFSCLK	53

#define SCU0_CLK_GATE_EMMCCLK	54

#define SCU0_CLK_GATE_RVAS1CLK	55

#define SCU0_CLK_U2PHY_REFCLKSRC 56

#define SCU0_CLK_AHBMUX			57

#define SCU0_CLK_MPHYSRC		58



/* SOC1 clk */

#define SCU1_CLKIN		0
@@ -159,5 +162,6 @@ 
#define SCU1_CLK_GATE_PORTCUSB2CLK	84

#define SCU1_CLK_GATE_PORTDUSB2CLK	85

#define SCU1_CLK_GATE_LTPI1TXCLK	86

#define SCU1_CLK_I3C				87



#endif