Commit 8efa26fc authored Jun 25, 2025 by Simon Horman Committed by David S. Miller Jun 27, 2025

tg3: spelling corrections



Correct spelling as flagged by codespell.

Signed-off-by: Simon Horman <horms@kernel.org>
Reviewed-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent 67e3ba97

drivers/net/ethernet/broadcom/tg3.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -6686,7 +6686,7 @@ static void tg3_rx_data_free(struct tg3 tp, struct ring_info ri, u32 map_sz)
		* We only need to fill in the address because the other members
		* of the RX descriptor are invariant, see tg3_init_rings.
		*
		* Note the purposeful assymetry of cpu vs. chip accesses. For
		* Note the purposeful asymmetry of cpu vs. chip accesses. For
		* posting buffers we only dirty the first cache line of the RX
		* descriptor (containing the address). Whereas for the RX status
		* buffers the cpu only reads the last cacheline of the RX descriptor
		@@ -10145,7 +10145,7 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
		tp->grc_mode \|= GRC_MODE_HOST_SENDBDS;

		/* Pseudo-header checksum is done by hardware logic and not
		* the offload processers, so make the chip do the pseudo-
		* the offload processors, so make the chip do the pseudo-
		* header checksums on receive. For transmit it is more
		* convenient to do the pseudo-header checksum in software
		* as Linux does that on transmit for us in all cases.

drivers/net/ethernet/broadcom/tg3.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -2390,7 +2390,7 @@
		#define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004


		/* Fast Ethernet Tranceiver definitions */
		/* Fast Ethernet Transceiver definitions */
		#define MII_TG3_FET_PTEST 0x17
		#define MII_TG3_FET_PTEST_TRIM_SEL 0x0010
		#define MII_TG3_FET_PTEST_TRIM_2 0x0002