Commit 8fbf3d47 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-imx-6.15' of... 

Merge tag 'clk-imx-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx

Pull i.MX clk driver updates from Abel Vesa:

 - Add missing AXI clock to the i.MX8MP AUDIOMIX in dt-bindings schema
 - Fix DSP and OCRAM_A parent clocks in i.MX8MP AUDIOMIX clock provider
 - Document vendor specific operating-mode property in i.MX8M clock
   provider dt-bindings schema
 - Apply overdrive/nominal constraints based on DT property in i.MX8MP
   clock provider

* tag 'clk-imx-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
  clk: imx8mp: inform CCF of maximum frequency of clocks
  dt-bindings: clock: imx8m: document nominal/overdrive properties
  clk: clk-imx8mp-audiomix: fix dsp/ocram_a clock parents
  dt-bindings: clock: imx8mp: add axi clock
parents 2014c95a 06a61b5c

Documentation/devicetree/bindings/clock/imx8m-clock.yaml

+8 −0
Original line number Diff line number Diff line
@@ -43,6 +43,13 @@ properties: 
      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h

      for the full list of i.MX8M clock IDs.



  fsl,operating-mode:

    $ref: /schemas/types.yaml#/definitions/string

    enum: [nominal, overdrive]

    description:

      The operating mode of the SoC. This affects the maximum clock rates that

      can safely be configured by the clock controller.



required:

  - compatible

  - reg
@@ -109,6 +116,7 @@ examples: 
                 <&clk_ext3>, <&clk_ext4>;

        clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",

                      "clk_ext3", "clk_ext4";

        fsl,operating-mode = "nominal";

    };



  - |

Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml

+6 −4
Original line number Diff line number Diff line
@@ -24,8 +24,8 @@ properties: 
    maxItems: 1



  clocks:

    minItems: 7

    maxItems: 7

    minItems: 8

    maxItems: 8



  clock-names:

    items:
@@ -36,6 +36,7 @@ properties: 
      - const: sai5

      - const: sai6

      - const: sai7

      - const: axi



  '#clock-cells':

    const: 1
@@ -72,10 +73,11 @@ examples: 
                 <&clk IMX8MP_CLK_SAI3>,

                 <&clk IMX8MP_CLK_SAI5>,

                 <&clk IMX8MP_CLK_SAI6>,

                 <&clk IMX8MP_CLK_SAI7>;

                 <&clk IMX8MP_CLK_SAI7>,

                 <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>;

        clock-names = "ahb",

                      "sai1", "sai2", "sai3",

                      "sai5", "sai6", "sai7";

                      "sai5", "sai6", "sai7", "axi";

        power-domains = <&pgc_audio>;

    };

drivers/clk/imx/clk-imx8mp-audiomix.c

+3 −3
Original line number Diff line number Diff line
@@ -180,14 +180,14 @@ static struct clk_imx8mp_audiomix_sel sels[] = { 
	CLK_GATE("asrc", ASRC_IPG),

	CLK_GATE("pdm", PDM_IPG),

	CLK_GATE("earc", EARC_IPG),

	CLK_GATE("ocrama", OCRAMA_IPG),

	CLK_GATE_PARENT("ocrama", OCRAMA_IPG, "axi"),

	CLK_GATE("aud2htx", AUD2HTX_IPG),

	CLK_GATE_PARENT("earc_phy", EARC_PHY, "sai_pll_out_div2"),

	CLK_GATE("sdma2", SDMA2_ROOT),

	CLK_GATE("sdma3", SDMA3_ROOT),

	CLK_GATE("spba2", SPBA2_ROOT),

	CLK_GATE("dsp", DSP_ROOT),

	CLK_GATE("dspdbg", DSPDBG_ROOT),

	CLK_GATE_PARENT("dsp", DSP_ROOT, "axi"),

	CLK_GATE_PARENT("dspdbg", DSPDBG_ROOT, "axi"),

	CLK_GATE("edma", EDMA_ROOT),

	CLK_GATE_PARENT("audpll", AUDPLL_ROOT, "osc_24m"),

	CLK_GATE("mu2", MU2_ROOT),

drivers/clk/imx/clk-imx8mp.c

+151 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <linux/err.h>

#include <linux/io.h>

#include <linux/module.h>

#include <linux/units.h>

#include <linux/of_address.h>

#include <linux/platform_device.h>

#include <linux/slab.h>
@@ -406,11 +407,151 @@ static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_ 
static struct clk_hw **hws;

static struct clk_hw_onecell_data *clk_hw_data;



struct imx8mp_clock_constraints {

	unsigned int clkid;

	u32 maxrate;

};



/*

 * Below tables are taken from IMX8MPCEC Rev. 2.1, 07/2023

 * Table 13. Maximum frequency of modules.

 * Probable typos fixed are marked with a comment.

 */

static const struct imx8mp_clock_constraints imx8mp_clock_common_constraints[] = {

	{ IMX8MP_CLK_A53_DIV,             1000 * HZ_PER_MHZ },

	{ IMX8MP_CLK_ENET_AXI,             266666667 }, /* Datasheet claims 266MHz */

	{ IMX8MP_CLK_NAND_USDHC_BUS,       266666667 }, /* Datasheet claims 266MHz */

	{ IMX8MP_CLK_MEDIA_APB,            200 * HZ_PER_MHZ },

	{ IMX8MP_CLK_HDMI_APB,             133333333 }, /* Datasheet claims 133MHz */

	{ IMX8MP_CLK_ML_AXI,               800 * HZ_PER_MHZ },

	{ IMX8MP_CLK_AHB,                  133333333 },

	{ IMX8MP_CLK_IPG_ROOT,              66666667 },

	{ IMX8MP_CLK_AUDIO_AHB,            400 * HZ_PER_MHZ },

	{ IMX8MP_CLK_MEDIA_DISP2_PIX,      170 * HZ_PER_MHZ },

	{ IMX8MP_CLK_DRAM_ALT,             666666667 },

	{ IMX8MP_CLK_DRAM_APB,             200 * HZ_PER_MHZ },

	{ IMX8MP_CLK_CAN1,                  80 * HZ_PER_MHZ },

	{ IMX8MP_CLK_CAN2,                  80 * HZ_PER_MHZ },

	{ IMX8MP_CLK_PCIE_AUX,              10 * HZ_PER_MHZ },

	{ IMX8MP_CLK_I2C5,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_I2C6,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_SAI1,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_SAI2,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_SAI3,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_SAI5,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_SAI6,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_ENET_QOS,             125 * HZ_PER_MHZ },

	{ IMX8MP_CLK_ENET_QOS_TIMER,       200 * HZ_PER_MHZ },

	{ IMX8MP_CLK_ENET_REF,             125 * HZ_PER_MHZ },

	{ IMX8MP_CLK_ENET_TIMER,           125 * HZ_PER_MHZ },

	{ IMX8MP_CLK_ENET_PHY_REF,         125 * HZ_PER_MHZ },

	{ IMX8MP_CLK_NAND,                 500 * HZ_PER_MHZ },

	{ IMX8MP_CLK_QSPI,                 400 * HZ_PER_MHZ },

	{ IMX8MP_CLK_USDHC1,               400 * HZ_PER_MHZ },

	{ IMX8MP_CLK_USDHC2,               400 * HZ_PER_MHZ },

	{ IMX8MP_CLK_I2C1,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_I2C2,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_I2C3,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_I2C4,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_UART1,                 80 * HZ_PER_MHZ },

	{ IMX8MP_CLK_UART2,                 80 * HZ_PER_MHZ },

	{ IMX8MP_CLK_UART3,                 80 * HZ_PER_MHZ },

	{ IMX8MP_CLK_UART4,                 80 * HZ_PER_MHZ },

	{ IMX8MP_CLK_ECSPI1,                80 * HZ_PER_MHZ },

	{ IMX8MP_CLK_ECSPI2,                80 * HZ_PER_MHZ },

	{ IMX8MP_CLK_PWM1,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_PWM2,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_PWM3,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_PWM4,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_GPT1,                 100 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPT2,                 100 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPT3,                 100 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPT4,                 100 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPT5,                 100 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPT6,                 100 * HZ_PER_MHZ },

	{ IMX8MP_CLK_WDOG,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_IPP_DO_CLKO1,         200 * HZ_PER_MHZ },

	{ IMX8MP_CLK_IPP_DO_CLKO2,         200 * HZ_PER_MHZ },

	{ IMX8MP_CLK_HDMI_REF_266M,        266 * HZ_PER_MHZ },

	{ IMX8MP_CLK_USDHC3,               400 * HZ_PER_MHZ },

	{ IMX8MP_CLK_MEDIA_MIPI_PHY1_REF,  300 * HZ_PER_MHZ },

	{ IMX8MP_CLK_MEDIA_DISP1_PIX,      250 * HZ_PER_MHZ },

	{ IMX8MP_CLK_MEDIA_CAM2_PIX,       277 * HZ_PER_MHZ },

	{ IMX8MP_CLK_MEDIA_LDB,            595 * HZ_PER_MHZ },

	{ IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE, 200 * HZ_PER_MHZ },

	{ IMX8MP_CLK_ECSPI3,                80 * HZ_PER_MHZ },

	{ IMX8MP_CLK_PDM,                  200 * HZ_PER_MHZ },

	{ IMX8MP_CLK_SAI7,                  66666667 }, /* Datasheet claims 66MHz */

	{ IMX8MP_CLK_MAIN_AXI,             400 * HZ_PER_MHZ },

	{ /* Sentinel */ }

};



static const struct imx8mp_clock_constraints imx8mp_clock_nominal_constraints[] = {

	{ IMX8MP_CLK_M7_CORE,           600 * HZ_PER_MHZ },

	{ IMX8MP_CLK_ML_CORE,           800 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPU3D_CORE,        800 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPU3D_SHADER_CORE, 800 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPU2D_CORE,        800 * HZ_PER_MHZ },

	{ IMX8MP_CLK_AUDIO_AXI_SRC,     600 * HZ_PER_MHZ },

	{ IMX8MP_CLK_HSIO_AXI,          400 * HZ_PER_MHZ },

	{ IMX8MP_CLK_MEDIA_ISP,         400 * HZ_PER_MHZ },

	{ IMX8MP_CLK_VPU_BUS,           600 * HZ_PER_MHZ },

	{ IMX8MP_CLK_MEDIA_AXI,         400 * HZ_PER_MHZ },

	{ IMX8MP_CLK_HDMI_AXI,          400 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPU_AXI,           600 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPU_AHB,           300 * HZ_PER_MHZ },

	{ IMX8MP_CLK_NOC,               800 * HZ_PER_MHZ },

	{ IMX8MP_CLK_NOC_IO,            600 * HZ_PER_MHZ },

	{ IMX8MP_CLK_ML_AHB,            300 * HZ_PER_MHZ },

	{ IMX8MP_CLK_VPU_G1,            600 * HZ_PER_MHZ },

	{ IMX8MP_CLK_VPU_G2,            500 * HZ_PER_MHZ },

	{ IMX8MP_CLK_MEDIA_CAM1_PIX,    400 * HZ_PER_MHZ },

	{ IMX8MP_CLK_VPU_VC8000E,       400 * HZ_PER_MHZ }, /* Datasheet claims 500MHz */

	{ IMX8MP_CLK_DRAM_CORE,         800 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GIC,               400 * HZ_PER_MHZ },

	{ /* Sentinel */ }

};



static const struct imx8mp_clock_constraints imx8mp_clock_overdrive_constraints[] = {

	{ IMX8MP_CLK_M7_CORE,            800 * HZ_PER_MHZ},

	{ IMX8MP_CLK_ML_CORE,           1000 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPU3D_CORE,        1000 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPU3D_SHADER_CORE, 1000 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPU2D_CORE,        1000 * HZ_PER_MHZ },

	{ IMX8MP_CLK_AUDIO_AXI_SRC,      800 * HZ_PER_MHZ },

	{ IMX8MP_CLK_HSIO_AXI,           500 * HZ_PER_MHZ },

	{ IMX8MP_CLK_MEDIA_ISP,          500 * HZ_PER_MHZ },

	{ IMX8MP_CLK_VPU_BUS,            800 * HZ_PER_MHZ },

	{ IMX8MP_CLK_MEDIA_AXI,          500 * HZ_PER_MHZ },

	{ IMX8MP_CLK_HDMI_AXI,           500 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPU_AXI,            800 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GPU_AHB,            400 * HZ_PER_MHZ },

	{ IMX8MP_CLK_NOC,               1000 * HZ_PER_MHZ },

	{ IMX8MP_CLK_NOC_IO,             800 * HZ_PER_MHZ },

	{ IMX8MP_CLK_ML_AHB,             400 * HZ_PER_MHZ },

	{ IMX8MP_CLK_VPU_G1,             800 * HZ_PER_MHZ },

	{ IMX8MP_CLK_VPU_G2,             700 * HZ_PER_MHZ },

	{ IMX8MP_CLK_MEDIA_CAM1_PIX,     500 * HZ_PER_MHZ },

	{ IMX8MP_CLK_VPU_VC8000E,        500 * HZ_PER_MHZ }, /* Datasheet claims 400MHz */

	{ IMX8MP_CLK_DRAM_CORE,         1000 * HZ_PER_MHZ },

	{ IMX8MP_CLK_GIC,                500 * HZ_PER_MHZ },

	{ /* Sentinel */ }

};



static void imx8mp_clocks_apply_constraints(const struct imx8mp_clock_constraints constraints[])

{

	const struct imx8mp_clock_constraints *constr;



	for (constr = constraints; constr->clkid; constr++)

		clk_hw_set_rate_range(hws[constr->clkid], 0, constr->maxrate);

}



static int imx8mp_clocks_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct device_node *np;

	void __iomem *anatop_base, *ccm_base;

	const char *opmode;

	int err;



	np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
@@ -715,6 +856,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) 


	imx_check_clk_hws(hws, IMX8MP_CLK_END);



	imx8mp_clocks_apply_constraints(imx8mp_clock_common_constraints);



	err = of_property_read_string(np, "fsl,operating-mode", &opmode);

	if (!err) {

		if (!strcmp(opmode, "nominal"))

			imx8mp_clocks_apply_constraints(imx8mp_clock_nominal_constraints);

		else if (!strcmp(opmode, "overdrive"))

			imx8mp_clocks_apply_constraints(imx8mp_clock_overdrive_constraints);

	}



	err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);

	if (err < 0) {

		dev_err(dev, "failed to register hws for i.MX8MP\n");