Commit 8fe44c08 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN 



No need for a separate flag now that DCN3.1 is not in bring up.
Fold into DRM_AMD_DC_DCN like previous DCN IPs.

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 519424d7

drivers/gpu/drm/amd/display/Kconfig

+0 −7
Original line number Diff line number Diff line
@@ -31,13 +31,6 @@ config DRM_AMD_DC_SI 
	  by default. This includes Tahiti, Pitcairn, Cape Verde, Oland.

	  Hainan is not supported by AMD DC and it has no physical DCE6.



config DRM_AMD_DC_DCN3_1

        bool "DCN 3.1 family"

        depends on DRM_AMD_DC_DCN

        help

            Choose this option if you want to have

            DCN3.1 family support for display engine



config DEBUG_KERNEL_DC

	bool "Enable kgdb break in DC"

	depends on DRM_AMD_DC

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+1 −21
Original line number Diff line number Diff line
@@ -110,10 +110,8 @@ MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 
MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);

#define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"

MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

#define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"

MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);

#endif



#define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"

MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -1145,16 +1143,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) 
		if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))

			init_data.flags.disable_dmcu = true;

		break;

#if defined(CONFIG_DRM_AMD_DC_DCN)

	case CHIP_VANGOGH:

		init_data.flags.gpu_vm_support = true;

		break;

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	case CHIP_YELLOW_CARP:

		init_data.flags.gpu_vm_support = true;

		break;

#endif

	default:

		break;

	}
@@ -1411,9 +1403,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev) 
	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

	case CHIP_VANGOGH:

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	case CHIP_YELLOW_CARP:

#endif

		return 0;

	case CHIP_NAVI12:

		fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
@@ -1532,12 +1522,10 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) 
		dmub_asic = DMUB_ASIC_DCN303;

		fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;

		break;

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	case CHIP_YELLOW_CARP:

		dmub_asic = DMUB_ASIC_DCN31;

		fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;

		break;

#endif



	default:

		/* ASIC doesn't support DMUB. */
@@ -2232,7 +2220,7 @@ static int dm_resume(void *handle) 
					= 0xffffffff;

			}

		}

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

#if defined(CONFIG_DRM_AMD_DC_DCN)

		/*

		 * Resource allocation happens for link encoders for newer ASIC in

		 * dc_validate_global_state, so we need to revalidate it.
@@ -3786,9 +3774,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 
	switch (adev->asic_type) {

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	case CHIP_YELLOW_CARP:

#endif

	case CHIP_RENOIR:

		if (register_outbox_irq_handlers(dm->adev)) {

			DRM_ERROR("DM: Failed to initialize IRQ\n");
@@ -3893,9 +3879,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 
	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

	case CHIP_VANGOGH:

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	case CHIP_YELLOW_CARP:

#endif

		if (dcn10_register_irq_handlers(dm->adev)) {

			DRM_ERROR("DM: Failed to initialize IRQ\n");

			goto fail;
@@ -4067,13 +4051,11 @@ static int dm_early_init(void *handle) 
		adev->mode_info.num_hpd = 6;

		adev->mode_info.num_dig = 6;

		break;

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	case CHIP_YELLOW_CARP:

		adev->mode_info.num_crtc = 4;

		adev->mode_info.num_hpd = 4;

		adev->mode_info.num_dig = 4;

		break;

#endif

	case CHIP_NAVI14:

	case CHIP_DIMGREY_CAVEFISH:

		adev->mode_info.num_crtc = 5;
@@ -4311,9 +4293,7 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev, 
	    adev->asic_type == CHIP_NAVY_FLOUNDER ||

	    adev->asic_type == CHIP_DIMGREY_CAVEFISH ||

	    adev->asic_type == CHIP_BEIGE_GOBY ||

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	    adev->asic_type == CHIP_YELLOW_CARP ||

#endif

	    adev->asic_type == CHIP_VANGOGH)

		tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;

}

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

+0 −4
Original line number Diff line number Diff line
@@ -467,13 +467,11 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) 
	display->dig_fe = config->dig_fe;

	link->dig_be = config->dig_be;

	link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	display->stream_enc_idx = config->stream_enc_idx;

	link->link_enc_idx = config->link_enc_idx;

	link->phy_idx = config->phy_idx;

	link->hdcp_supported_informational = dc_link_is_hdcp14(aconnector->dc_link,

			aconnector->dc_sink->sink_signal) ? 1 : 0;

#endif

	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;

	link->dp.assr_enabled = config->assr_enabled;

	link->dp.mst_enabled = config->mst_enabled;
@@ -657,12 +655,10 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct 
		INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate);



		hdcp_work[i].hdcp.config.psp.handle = &adev->psp;

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

		if (dc->ctx->dce_version == DCN_VERSION_3_1) {

			hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;

			hdcp_work[i].hdcp.config.psp.caps.opm_state_query_supported = false;

		}

#endif

		hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);

		hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;

		hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;

drivers/gpu/drm/amd/display/dc/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -34,10 +34,8 @@ DC_LIBS += dcn30 
DC_LIBS += dcn301

DC_LIBS += dcn302

DC_LIBS += dcn303

ifdef CONFIG_DRM_AMD_DC_DCN3_1

DC_LIBS += dcn31

endif

endif



DC_LIBS += dce120

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

+1 −6
Original line number Diff line number Diff line
@@ -576,13 +576,11 @@ static struct device_id device_type_from_device_id(uint16_t device_id) 
		result_device_id.device_type = DEVICE_TYPE_LCD;

		result_device_id.enum_id = 1;

		break;

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)



	case ATOM_DISPLAY_LCD2_SUPPORT:

		result_device_id.device_type = DEVICE_TYPE_LCD;

		result_device_id.enum_id = 2;

		break;

#endif



	case ATOM_DISPLAY_DFP1_SUPPORT:

		result_device_id.device_type = DEVICE_TYPE_DFP;
@@ -2162,7 +2160,6 @@ static enum bp_result get_integrated_info_v2_1( 
	return BP_RESULT_OK;

}



#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

static enum bp_result get_integrated_info_v2_2(

	struct bios_parser *bp,

	struct integrated_info *info)
@@ -2262,7 +2259,7 @@ static enum bp_result get_integrated_info_v2_2( 


	return BP_RESULT_OK;

}

#endif



/*

 * construct_integrated_info

 *
@@ -2310,11 +2307,9 @@ static enum bp_result construct_integrated_info( 
			case 1:

				result = get_integrated_info_v2_1(bp, info);

				break;

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

			case 2:

				result = get_integrated_info_v2_2(bp, info);

				break;

#endif

			default:

				return result;

			}