Commit 8fff7ae8 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Jakub Kicinski
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dt-bindings: net: Document support for Renesas RZ/V2H(P) GBETH 



GBETH IP on the Renesas RZ/V2H(P) SoC is integrated with Synopsys
DesignWare MAC (version 5.20). Document the device tree bindings for
the GBETH glue layer.

Generic compatible string 'renesas,rzv2h-gbeth' is added since this
module is identical on both the RZ/V2H(P) and RZ/G3E SoCs.

The Rx/Tx clocks supplied for GBETH on the RZ/V2H(P) SoC is depicted
below:

                      Rx / Tx
-------+------------- on / off -------
       |
       |            Rx-180 / Tx-180
       +---- not ---- on / off -------

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250417084015.74154-3-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 8c989368

Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: GBETH glue layer for Renesas RZ/V2H(P) (and similar SoCs)



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



select:

  properties:

    compatible:

      contains:

        enum:

          - renesas,r9a09g057-gbeth

          - renesas,rzv2h-gbeth

  required:

    - compatible



properties:

  compatible:

    items:

      - enum:

          - renesas,r9a09g057-gbeth # RZ/V2H(P)

      - const: renesas,rzv2h-gbeth

      - const: snps,dwmac-5.20



  reg:

    maxItems: 1



  clocks:

    items:

      - description: CSR clock

      - description: AXI system clock

      - description: PTP clock

      - description: TX clock

      - description: RX clock

      - description: TX clock phase-shifted by 180 degrees

      - description: RX clock phase-shifted by 180 degrees



  clock-names:

    items:

      - const: stmmaceth

      - const: pclk

      - const: ptp_ref

      - const: tx

      - const: rx

      - const: tx-180

      - const: rx-180



  interrupts:

    minItems: 11



  interrupt-names:

    items:

      - const: macirq

      - const: eth_wake_irq

      - const: eth_lpi

      - const: rx-queue-0

      - const: rx-queue-1

      - const: rx-queue-2

      - const: rx-queue-3

      - const: tx-queue-0

      - const: tx-queue-1

      - const: tx-queue-2

      - const: tx-queue-3



  resets:

    items:

      - description: AXI power-on system reset



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - interrupts

  - interrupt-names

  - resets



allOf:

  - $ref: snps,dwmac.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/renesas-cpg-mssr.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    ethernet@15c30000 {

        compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20";

        reg = <0x15c30000 0x10000>;

        clocks =  <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,

                  <&ptp_clock>, <&cpg CPG_MOD 0xb8>,

                  <&cpg CPG_MOD 0xb9>, <&cpg CPG_MOD 0xba>,

                  <&cpg CPG_MOD 0xbb>;

        clock-names = "stmmaceth", "pclk", "ptp_ref",

                      "tx", "rx", "tx-180", "rx-180";

        resets = <&cpg 0xb0>;

        interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",

                          "rx-queue-0", "rx-queue-1", "rx-queue-2",

                          "rx-queue-3", "tx-queue-0", "tx-queue-1",

                          "tx-queue-2", "tx-queue-3";

        phy-mode = "rgmii-id";

        snps,multicast-filter-bins = <256>;

        snps,perfect-filter-entries = <128>;

        rx-fifo-depth = <8192>;

        tx-fifo-depth = <8192>;

        snps,fixed-burst;

        snps,force_thresh_dma_mode;

        snps,axi-config = <&stmmac_axi_setup>;

        snps,mtl-rx-config = <&mtl_rx_setup>;

        snps,mtl-tx-config = <&mtl_tx_setup>;

        snps,txpbl = <32>;

        snps,rxpbl = <32>;

        phy-handle = <&phy0>;



        stmmac_axi_setup: stmmac-axi-config {

            snps,lpi_en;

            snps,wr_osr_lmt = <0xf>;

            snps,rd_osr_lmt = <0xf>;

            snps,blen = <16 8 4 0 0 0 0>;

        };



        mtl_rx_setup: rx-queues-config {

            snps,rx-queues-to-use = <4>;

            snps,rx-sched-sp;



            queue0 {

                snps,dcb-algorithm;

                snps,priority = <0x1>;

                snps,map-to-dma-channel = <0>;

            };



            queue1 {

                snps,dcb-algorithm;

                snps,priority = <0x2>;

                snps,map-to-dma-channel = <1>;

            };



            queue2 {

                snps,dcb-algorithm;

                snps,priority = <0x4>;

                snps,map-to-dma-channel = <2>;

            };



            queue3 {

                snps,dcb-algorithm;

                snps,priority = <0x8>;

                snps,map-to-dma-channel = <3>;

            };

        };



        mtl_tx_setup: tx-queues-config {

            snps,tx-queues-to-use = <4>;



            queue0 {

                snps,dcb-algorithm;

                snps,priority = <0x1>;

            };



            queue1 {

                snps,dcb-algorithm;

                snps,priority = <0x2>;

            };



            queue2 {

                snps,dcb-algorithm;

                snps,priority = <0x4>;

            };



            queue3 {

                snps,dcb-algorithm;

                snps,priority = <0x1>;

            };

        };



        mdio {

            #address-cells = <1>;

            #size-cells = <0>;

            compatible = "snps,dwmac-mdio";



            phy0: ethernet-phy@0 {

                reg = <0>;

            };

        };

    };

Documentation/devicetree/bindings/net/snps,dwmac.yaml

+1 −0
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ properties: 
        - qcom,sm8150-ethqos

        - renesas,r9a06g032-gmac

        - renesas,rzn1-gmac

        - renesas,rzv2h-gbeth

        - rockchip,px30-gmac

        - rockchip,rk3128-gmac

        - rockchip,rk3228-gmac