Commit 9045512c authored by Vadim Pasternak's avatar Vadim Pasternak Committed by Hans de Goede
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platform/x86: mlx-platform: Extend FAN and LED configuration to support new MQM97xx systems 



Add support for new system types "MQM97xx", which is based on Mellanox
Quantum-2 ASIC. It provides up to 64x400GB/s (IB) full bidirectional
bandwidth per port using PAM-4 modulation. The system support 32 OSFP
cages that can provide 64x400GB/s per port (two ports/cage). The system
fits standard 1U racks.

System is equipped with seven fan drawers and with per fan drawer LED
on backport panel and uses two-bytes for exposing CPLD Part Number
versions.

System is recognized by "DMI_BOARD_NAME" match, when this field is set
to "VMOD0010".

Signed-off-by: default avatarVadim Pasternak <vadimp@nvidia.com>
Reviewed-by: default avatarOleksandr Shamray <oleksandrs@nvidia.com>
Link: https://lore.kernel.org/r/20211023094022.4193813-2-vadimp@nvidia.com


Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 3aa539a5

drivers/platform/x86/mlx-platform.c

+55 −1
Original line number Diff line number Diff line
@@ -27,9 +27,13 @@ 
#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET	0x02

#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET	0x03

#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET	0x04

#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET	0x05

#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET	0x06

#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET	0x07

#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET	0x08

#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET	0x09

#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET	0x0a

#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET	0x0b

#define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET	0x1c

#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET	0x1d

#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET	0x1e
@@ -127,6 +131,8 @@ 
#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET	0xee

#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET	0xef

#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET	0xf0

#define MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET	0xf1

#define MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET	0xf2

#define MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET	0xf3

#define MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET	0xf4

#define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET	0xf5
@@ -194,7 +200,7 @@ 
#define MLXPLAT_CPLD_PWR_EXT_MASK	GENMASK(3, 0)

#define MLXPLAT_CPLD_FAN_MASK		GENMASK(3, 0)

#define MLXPLAT_CPLD_ASIC_MASK		GENMASK(1, 0)

#define MLXPLAT_CPLD_FAN_NG_MASK	GENMASK(5, 0)

#define MLXPLAT_CPLD_FAN_NG_MASK	GENMASK(6, 0)

#define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK	GENMASK(7, 4)

#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK	GENMASK(3, 0)

#define MLXPLAT_CPLD_VOLTREG_UPD_MASK	GENMASK(5, 4)
@@ -933,6 +939,14 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = { 
		.bit = BIT(5),

		.hpdev.nr = MLXPLAT_CPLD_NR_NONE,

	},

	{

		.label = "fan7",

		.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,

		.mask = BIT(6),

		.capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,

		.bit = BIT(6),

		.hpdev.nr = MLXPLAT_CPLD_NR_NONE,

	},

};



static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = {
@@ -2164,6 +2178,20 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { 
		.capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,

		.bit = BIT(5),

	},

	{

		.label = "fan7:green",

		.reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,

		.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,

		.capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,

		.bit = BIT(6),

	},

	{

		.label = "fan7:orange",

		.reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,

		.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,

		.capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,

		.bit = BIT(6),

	},

	{

		.label = "uid:blue",

		.reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
@@ -3526,6 +3554,20 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { 
		.bit = BIT(3),

		.reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,

	},

	{

		.label = "tacho13",

		.reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET,

		.mask = GENMASK(7, 0),

		.capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,

		.bit = BIT(4),

	},

	{

		.label = "tacho14",

		.reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET,

		.mask = GENMASK(7, 0),

		.capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,

		.bit = BIT(5),

	},

	{

		.label = "conf",

		.capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET,
@@ -3835,9 +3877,13 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 
	case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
@@ -3935,6 +3981,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 
	case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
@@ -3958,9 +4006,13 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 
	case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
@@ -4050,6 +4102,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 
	case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: