Commit 90cf94ed authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v6.7-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk driver updates from Jerome Brunet:

 - Add s4 main clock controller support

* tag 'clk-meson-v6.7-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller
  clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
  dt-bindings: clock: document Amlogic S4 SoC peripherals clock controller
  dt-bindings: clock: document Amlogic S4 SoC PLL clock controller
parents 0bb80ecc 57b55c76

Documentation/devicetree/bindings/clock/amlogic,s4-peripherals-clkc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,s4-peripherals-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic S4 Peripherals Clock Controller



maintainers:

  - Yu Tu <yu.tu@amlogic.com>



properties:

  compatible:

    const: amlogic,s4-peripherals-clkc



  reg:

    maxItems: 1



  clocks:

    minItems: 14

    items:

      - description: input fixed pll div2

      - description: input fixed pll div2p5

      - description: input fixed pll div3

      - description: input fixed pll div4

      - description: input fixed pll div5

      - description: input fixed pll div7

      - description: input hifi pll

      - description: input gp0 pll

      - description: input mpll0

      - description: input mpll1

      - description: input mpll2

      - description: input mpll3

      - description: input hdmi pll

      - description: input oscillator (usually at 24MHz)

      - description: input external 32kHz reference (optional)



  clock-names:

    minItems: 14

    items:

      - const: fclk_div2

      - const: fclk_div2p5

      - const: fclk_div3

      - const: fclk_div4

      - const: fclk_div5

      - const: fclk_div7

      - const: hifi_pll

      - const: gp0_pll

      - const: mpll0

      - const: mpll1

      - const: mpll2

      - const: mpll3

      - const: hdmi_pll

      - const: xtal

      - const: ext_32k



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>



    clkc_periphs: clock-controller@fe000000 {

      compatible = "amlogic,s4-peripherals-clkc";

      reg = <0xfe000000 0x49c>;

      clocks = <&clkc_pll 3>,

              <&clkc_pll 13>,

              <&clkc_pll 5>,

              <&clkc_pll 7>,

              <&clkc_pll 9>,

              <&clkc_pll 11>,

              <&clkc_pll 17>,

              <&clkc_pll 15>,

              <&clkc_pll 25>,

              <&clkc_pll 27>,

              <&clkc_pll 29>,

              <&clkc_pll 31>,

              <&clkc_pll 20>,

              <&xtal>;

      clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", "fclk_div4",

                    "fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll",

                    "mpll0", "mpll1", "mpll2", "mpll3", "hdmi_pll", "xtal";

      #clock-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic S4 PLL Clock Controller



maintainers:

  - Yu Tu <yu.tu@amlogic.com>



properties:

  compatible:

    const: amlogic,s4-pll-clkc



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: xtal



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    clkc_pll: clock-controller@fe008000 {

      compatible = "amlogic,s4-pll-clkc";

      reg = <0xfe008000 0x1e8>;

      clocks = <&xtal>;

      clock-names = "xtal";

      #clock-cells = <1>;

    };



...

drivers/clk/meson/Kconfig

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@@ -144,4 +144,27 @@ config COMMON_CLK_G12A 
	help

	  Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2

	  devices, aka g12a. Say Y if you want peripherals to work.



config COMMON_CLK_S4_PLL

	tristate "S4 SoC PLL clock controllers support"

	depends on ARM64

	default y

	select COMMON_CLK_MESON_MPLL

	select COMMON_CLK_MESON_PLL

	select COMMON_CLK_MESON_REGMAP

	help

	  Support for the PLL clock controller on Amlogic S805X2 and S905Y4 devices,

	  AKA S4. Say Y if you want the board to work, because PLLs are the parent of

	  most peripherals.



config COMMON_CLK_S4_PERIPHERALS

	tristate "S4 SoC peripherals clock controllers support"

	depends on ARM64

	default y

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_DUALDIV

	select COMMON_CLK_MESON_VID_PLL_DIV

	help

	  Support for the peripherals clock controller on Amlogic S805X2 and S905Y4

	  devices, AKA S4. Say Y if you want S4 peripherals clock controller to work.

endmenu

drivers/clk/meson/Makefile

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@@ -22,3 +22,5 @@ obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o 
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o

obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o

obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o

obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o

obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o

drivers/clk/meson/s4-peripherals.c

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