Commit 91bd7a44 authored by Uma Shankar's avatar Uma Shankar
Browse files

drm/i915/display/tgl: Disable FBC with PSR2 



There are some corner cases wrt underrun when we enable
FBC with PSR2 on TGL. Recommendation from hardware is to
keep this combination disabled.

Bspec: 50422 HSD: 14010260002

v2: Added psr2 enabled check from crtc_state (Anshuman)
Added Bspec link and HSD referneces (Jose)

v3: Moved the logic to disable fbc to intel_fbc_update_state_cache
and removed the crtc->config usages, as per Ville's recommendation.

v4: Introduced a variable in fbc state_cache instead of the earlier
plane.visible WA, as suggested by Jose.

v5: Dropped an extra check for fbc in intel_fbc_enable and addressed
review comments by Jose.

v6: Move WA to end of function and added Jose's RB.

Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201201190406.1752-2-uma.shankar@intel.com
parent ca3fb882

drivers/gpu/drm/i915/display/intel_fbc.c

+12 −0
Original line number Diff line number Diff line
@@ -742,6 +742,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, 
		cache->fence_id = plane_state->vma->fence->id;

	else

		cache->fence_id = -1;



	cache->psr2_active = crtc_state->has_psr2;

}



static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
@@ -914,6 +916,16 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) 
		return false;

	}



	/*

	 * Tigerlake is not supporting FBC with PSR2.

	 * Recommendation is to keep this combination disabled

	 * Bspec: 50422 HSD: 14010260002

	 */

	if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {

		fbc->no_fbc_reason = "not supported with PSR2";

		return false;

	}



	return true;

}

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -416,6 +416,7 @@ struct intel_fbc { 
		u16 gen9_wa_cfb_stride;

		u16 interval;

		s8 fence_id;

		bool psr2_active;

	} state_cache;



	/*