Unverified Commit 91c26854 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Mark Brown
Browse files

ASoC: mediatek: mt8183-afe-pcm: Shorten memif_data table using macros 



The memif_data table describes all the supported PCM channels for the
audio frontend. Most of the fields are either the same or can be derived
from the interface's name. This results in a very long table (in source
code) that can be shortened with macros.

Do just that. Some "convenience" macros were added to cover non-existent
register fields that would otherwise require multiple layers of macros
to handle.

Signed-off-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20250515073825.4155297-2-wenst@chromium.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 51590571

sound/soc/mediatek/mt8183/mt8183-afe-pcm.c

+54 −189
Original line number Diff line number Diff line
@@ -424,196 +424,61 @@ static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = { 
	.name = "mt8183-afe-pcm-dai",

};



#define MT8183_MEMIF_BASE(_id, _en_reg, _fs_reg, _mono_reg)    \

	[MT8183_MEMIF_##_id] = { \

		.name = #_id,				\

		.id = MT8183_MEMIF_##_id,		\

		.reg_ofs_base = AFE_##_id##_BASE,	\

		.reg_ofs_cur = AFE_##_id##_CUR,		\

		.reg_ofs_end = AFE_##_id##_END,		\

		.fs_reg = (_fs_reg),			\

		.fs_shift = _id##_MODE_SFT,		\

		.fs_maskbit = _id##_MODE_MASK,		\

		.mono_reg = (_mono_reg),		\

		.mono_shift = _id##_DATA_SFT,		\

		.enable_reg = (_en_reg),		\

		.enable_shift = _id##_ON_SFT,		\

		.hd_reg = AFE_MEMIF_HD_MODE,		\

		.hd_align_reg = AFE_MEMIF_HDALIGN,	\

		.hd_shift = _id##_HD_SFT,		\

		.hd_align_mshift = _id##_HD_ALIGN_SFT,	\

		.agent_disable_reg = -1,		\

		.agent_disable_shift = -1,		\

		.msb_reg = -1,				\

		.msb_shift = -1,			\

	}



#define MT8183_MEMIF(_id, _fs_reg, _mono_reg) \

		MT8183_MEMIF_BASE(_id, AFE_DAC_CON0, _fs_reg, _mono_reg)



/* For convenience with macros: missing register fields */

#define MOD_DAI_DATA_SFT	-1

#define HDMI_MODE_SFT		-1

#define HDMI_MODE_MASK		-1

#define HDMI_DATA_SFT		-1

#define HDMI_ON_SFT		-1



/* For convenience with macros: register name differences */

#define AFE_VUL12_BASE		AFE_VUL_D2_BASE

#define AFE_VUL12_CUR		AFE_VUL_D2_CUR

#define AFE_VUL12_END		AFE_VUL_D2_END

#define AWB2_HD_ALIGN_SFT	AWB2_ALIGN_SFT

#define VUL12_DATA_SFT		VUL12_MONO_SFT

#define AFE_HDMI_BASE		AFE_HDMI_OUT_BASE

#define AFE_HDMI_CUR		AFE_HDMI_OUT_CUR

#define AFE_HDMI_END		AFE_HDMI_OUT_END



static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {

	[MT8183_MEMIF_DL1] = {

		.name = "DL1",

		.id = MT8183_MEMIF_DL1,

		.reg_ofs_base = AFE_DL1_BASE,

		.reg_ofs_cur = AFE_DL1_CUR,

		.fs_reg = AFE_DAC_CON1,

		.fs_shift = DL1_MODE_SFT,

		.fs_maskbit = DL1_MODE_MASK,

		.mono_reg = AFE_DAC_CON1,

		.mono_shift = DL1_DATA_SFT,

		.enable_reg = AFE_DAC_CON0,

		.enable_shift = DL1_ON_SFT,

		.hd_reg = AFE_MEMIF_HD_MODE,

		.hd_align_reg = AFE_MEMIF_HDALIGN,

		.hd_shift = DL1_HD_SFT,

		.hd_align_mshift = DL1_HD_ALIGN_SFT,

		.agent_disable_reg = -1,

		.agent_disable_shift = -1,

		.msb_reg = -1,

		.msb_shift = -1,

	},

	[MT8183_MEMIF_DL2] = {

		.name = "DL2",

		.id = MT8183_MEMIF_DL2,

		.reg_ofs_base = AFE_DL2_BASE,

		.reg_ofs_cur = AFE_DL2_CUR,

		.fs_reg = AFE_DAC_CON1,

		.fs_shift = DL2_MODE_SFT,

		.fs_maskbit = DL2_MODE_MASK,

		.mono_reg = AFE_DAC_CON1,

		.mono_shift = DL2_DATA_SFT,

		.enable_reg = AFE_DAC_CON0,

		.enable_shift = DL2_ON_SFT,

		.hd_reg = AFE_MEMIF_HD_MODE,

		.hd_align_reg = AFE_MEMIF_HDALIGN,

		.hd_shift = DL2_HD_SFT,

		.hd_align_mshift = DL2_HD_ALIGN_SFT,

		.agent_disable_reg = -1,

		.agent_disable_shift = -1,

		.msb_reg = -1,

		.msb_shift = -1,

	},

	[MT8183_MEMIF_DL3] = {

		.name = "DL3",

		.id = MT8183_MEMIF_DL3,

		.reg_ofs_base = AFE_DL3_BASE,

		.reg_ofs_cur = AFE_DL3_CUR,

		.fs_reg = AFE_DAC_CON2,

		.fs_shift = DL3_MODE_SFT,

		.fs_maskbit = DL3_MODE_MASK,

		.mono_reg = AFE_DAC_CON1,

		.mono_shift = DL3_DATA_SFT,

		.enable_reg = AFE_DAC_CON0,

		.enable_shift = DL3_ON_SFT,

		.hd_reg = AFE_MEMIF_HD_MODE,

		.hd_align_reg = AFE_MEMIF_HDALIGN,

		.hd_shift = DL3_HD_SFT,

		.hd_align_mshift = DL3_HD_ALIGN_SFT,

		.agent_disable_reg = -1,

		.agent_disable_shift = -1,

		.msb_reg = -1,

		.msb_shift = -1,

	},

	[MT8183_MEMIF_VUL2] = {

		.name = "VUL2",

		.id = MT8183_MEMIF_VUL2,

		.reg_ofs_base = AFE_VUL2_BASE,

		.reg_ofs_cur = AFE_VUL2_CUR,

		.fs_reg = AFE_DAC_CON2,

		.fs_shift = VUL2_MODE_SFT,

		.fs_maskbit = VUL2_MODE_MASK,

		.mono_reg = AFE_DAC_CON2,

		.mono_shift = VUL2_DATA_SFT,

		.enable_reg = AFE_DAC_CON0,

		.enable_shift = VUL2_ON_SFT,

		.hd_reg = AFE_MEMIF_HD_MODE,

		.hd_align_reg = AFE_MEMIF_HDALIGN,

		.hd_shift = VUL2_HD_SFT,

		.hd_align_mshift = VUL2_HD_ALIGN_SFT,

		.agent_disable_reg = -1,

		.agent_disable_shift = -1,

		.msb_reg = -1,

		.msb_shift = -1,

	},

	[MT8183_MEMIF_AWB] = {

		.name = "AWB",

		.id = MT8183_MEMIF_AWB,

		.reg_ofs_base = AFE_AWB_BASE,

		.reg_ofs_cur = AFE_AWB_CUR,

		.fs_reg = AFE_DAC_CON1,

		.fs_shift = AWB_MODE_SFT,

		.fs_maskbit = AWB_MODE_MASK,

		.mono_reg = AFE_DAC_CON1,

		.mono_shift = AWB_DATA_SFT,

		.enable_reg = AFE_DAC_CON0,

		.enable_shift = AWB_ON_SFT,

		.hd_reg = AFE_MEMIF_HD_MODE,

		.hd_align_reg = AFE_MEMIF_HDALIGN,

		.hd_shift = AWB_HD_SFT,

		.hd_align_mshift = AWB_HD_ALIGN_SFT,

		.agent_disable_reg = -1,

		.agent_disable_shift = -1,

		.msb_reg = -1,

		.msb_shift = -1,

	},

	[MT8183_MEMIF_AWB2] = {

		.name = "AWB2",

		.id = MT8183_MEMIF_AWB2,

		.reg_ofs_base = AFE_AWB2_BASE,

		.reg_ofs_cur = AFE_AWB2_CUR,

		.fs_reg = AFE_DAC_CON2,

		.fs_shift = AWB2_MODE_SFT,

		.fs_maskbit = AWB2_MODE_MASK,

		.mono_reg = AFE_DAC_CON2,

		.mono_shift = AWB2_DATA_SFT,

		.enable_reg = AFE_DAC_CON0,

		.enable_shift = AWB2_ON_SFT,

		.hd_reg = AFE_MEMIF_HD_MODE,

		.hd_align_reg = AFE_MEMIF_HDALIGN,

		.hd_shift = AWB2_HD_SFT,

		.hd_align_mshift = AWB2_ALIGN_SFT,

		.agent_disable_reg = -1,

		.agent_disable_shift = -1,

		.msb_reg = -1,

		.msb_shift = -1,

	},

	[MT8183_MEMIF_VUL12] = {

		.name = "VUL12",

		.id = MT8183_MEMIF_VUL12,

		.reg_ofs_base = AFE_VUL_D2_BASE,

		.reg_ofs_cur = AFE_VUL_D2_CUR,

		.fs_reg = AFE_DAC_CON0,

		.fs_shift = VUL12_MODE_SFT,

		.fs_maskbit = VUL12_MODE_MASK,

		.mono_reg = AFE_DAC_CON0,

		.mono_shift = VUL12_MONO_SFT,

		.enable_reg = AFE_DAC_CON0,

		.enable_shift = VUL12_ON_SFT,

		.hd_reg = AFE_MEMIF_HD_MODE,

		.hd_align_reg = AFE_MEMIF_HDALIGN,

		.hd_shift = VUL12_HD_SFT,

		.hd_align_mshift = VUL12_HD_ALIGN_SFT,

		.agent_disable_reg = -1,

		.agent_disable_shift = -1,

		.msb_reg = -1,

		.msb_shift = -1,

	},

	[MT8183_MEMIF_MOD_DAI] = {

		.name = "MOD_DAI",

		.id = MT8183_MEMIF_MOD_DAI,

		.reg_ofs_base = AFE_MOD_DAI_BASE,

		.reg_ofs_cur = AFE_MOD_DAI_CUR,

		.fs_reg = AFE_DAC_CON1,

		.fs_shift = MOD_DAI_MODE_SFT,

		.fs_maskbit = MOD_DAI_MODE_MASK,

		.mono_reg = -1,

		.mono_shift = 0,

		.enable_reg = AFE_DAC_CON0,

		.enable_shift = MOD_DAI_ON_SFT,

		.hd_reg = AFE_MEMIF_HD_MODE,

		.hd_align_reg = AFE_MEMIF_HDALIGN,

		.hd_shift = MOD_DAI_HD_SFT,

		.hd_align_mshift = MOD_DAI_HD_ALIGN_SFT,

		.agent_disable_reg = -1,

		.agent_disable_shift = -1,

		.msb_reg = -1,

		.msb_shift = -1,

	},

	[MT8183_MEMIF_HDMI] = {

		.name = "HDMI",

		.id = MT8183_MEMIF_HDMI,

		.reg_ofs_base = AFE_HDMI_OUT_BASE,

		.reg_ofs_cur = AFE_HDMI_OUT_CUR,

		.fs_reg = -1,

		.fs_shift = -1,

		.fs_maskbit = -1,

		.mono_reg = -1,

		.mono_shift = -1,

		.enable_reg = -1,	/* control in tdm for sync start */

		.enable_shift = -1,

		.hd_reg = AFE_MEMIF_HD_MODE,

		.hd_align_reg = AFE_MEMIF_HDALIGN,

		.hd_shift = HDMI_HD_SFT,

		.hd_align_mshift = HDMI_HD_ALIGN_SFT,

		.agent_disable_reg = -1,

		.agent_disable_shift = -1,

		.msb_reg = -1,

		.msb_shift = -1,

	},

	MT8183_MEMIF(DL1, AFE_DAC_CON1, AFE_DAC_CON1),

	MT8183_MEMIF(DL2, AFE_DAC_CON1, AFE_DAC_CON1),

	MT8183_MEMIF(DL3, AFE_DAC_CON2, AFE_DAC_CON1),

	MT8183_MEMIF(VUL2, AFE_DAC_CON2, AFE_DAC_CON2),

	MT8183_MEMIF(AWB, AFE_DAC_CON1, AFE_DAC_CON1),

	MT8183_MEMIF(AWB2, AFE_DAC_CON2, AFE_DAC_CON2),

	MT8183_MEMIF(VUL12, AFE_DAC_CON0, AFE_DAC_CON0),

	MT8183_MEMIF(MOD_DAI, AFE_DAC_CON1, -1),

	/* enable control in tdm for sync start */

	MT8183_MEMIF_BASE(HDMI, -1, -1, -1),

};



static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {