Commit 92d04de2 authored by Varadarajan Narayanan's avatar Varadarajan Narayanan Committed by Bjorn Andersson
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clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks 



Use the icc-clk framework to enable few clocks to be able to
create paths and use the peripherals connected on those NoCs.

Remove CLK_IGNORE_UNUSED from gpll4_main as all consumers have
been identified.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarVaradarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20240730054817.1915652-5-quic_varada@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 0e1ac23d

drivers/clk/qcom/gcc-ipq5332.c

+24 −11
Original line number Diff line number Diff line
@@ -4,12 +4,14 @@ 
 */



#include <linux/clk-provider.h>

#include <linux/interconnect-provider.h>

#include <linux/mod_devicetable.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>



#include <dt-bindings/clock/qcom,ipq5332-gcc.h>

#include <dt-bindings/interconnect/qcom,ipq5332.h>



#include "clk-alpha-pll.h"

#include "clk-branch.h"
@@ -126,17 +128,6 @@ static struct clk_alpha_pll gpll4_main = { 
			.parent_data = &gcc_parent_data_xo,

			.num_parents = 1,

			.ops = &clk_alpha_pll_stromer_ops,

			/*

			 * There are no consumers for this GPLL in kernel yet,

			 * (will be added soon), so the clock framework

			 * disables this source. But some of the clocks

			 * initialized by boot loaders uses this source. So we

			 * need to keep this clock ON. Add the

			 * CLK_IGNORE_UNUSED flag so the clock will not be

			 * disabled. Once the consumer in kernel is added, we

			 * can get rid of this flag.

			 */

			.flags = CLK_IGNORE_UNUSED,

		},

	},

};
@@ -3629,6 +3620,24 @@ static const struct qcom_reset_map gcc_ipq5332_resets[] = { 
	[GCC_UNIPHY1_XPCS_ARES] = { 0x16060 },

};



#define IPQ_APPS_ID			5332	/* some unique value */



static struct qcom_icc_hws_data icc_ipq5332_hws[] = {

	{ MASTER_SNOC_PCIE3_1_M, SLAVE_SNOC_PCIE3_1_M, GCC_SNOC_PCIE3_1LANE_M_CLK },

	{ MASTER_ANOC_PCIE3_1_S, SLAVE_ANOC_PCIE3_1_S, GCC_SNOC_PCIE3_1LANE_S_CLK },

	{ MASTER_SNOC_PCIE3_2_M, SLAVE_SNOC_PCIE3_2_M, GCC_SNOC_PCIE3_2LANE_M_CLK },

	{ MASTER_ANOC_PCIE3_2_S, SLAVE_ANOC_PCIE3_2_S, GCC_SNOC_PCIE3_2LANE_S_CLK },

	{ MASTER_SNOC_USB, SLAVE_SNOC_USB, GCC_SNOC_USB_CLK },

	{ MASTER_NSSNOC_NSSCC, SLAVE_NSSNOC_NSSCC, GCC_NSSNOC_NSSCC_CLK },

	{ MASTER_NSSNOC_SNOC_0, SLAVE_NSSNOC_SNOC_0, GCC_NSSNOC_SNOC_CLK },

	{ MASTER_NSSNOC_SNOC_1, SLAVE_NSSNOC_SNOC_1, GCC_NSSNOC_SNOC_1_CLK },

	{ MASTER_NSSNOC_ATB, SLAVE_NSSNOC_ATB, GCC_NSSNOC_ATB_CLK },

	{ MASTER_NSSNOC_PCNOC_1, SLAVE_NSSNOC_PCNOC_1, GCC_NSSNOC_PCNOC_1_CLK },

	{ MASTER_NSSNOC_QOSGEN_REF, SLAVE_NSSNOC_QOSGEN_REF, GCC_NSSNOC_QOSGEN_REF_CLK },

	{ MASTER_NSSNOC_TIMEOUT_REF, SLAVE_NSSNOC_TIMEOUT_REF, GCC_NSSNOC_TIMEOUT_REF_CLK },

	{ MASTER_NSSNOC_XO_DCD, SLAVE_NSSNOC_XO_DCD, GCC_NSSNOC_XO_DCD_CLK },

};



static const struct regmap_config gcc_ipq5332_regmap_config = {

	.reg_bits = 32,

	.reg_stride = 4,
@@ -3657,6 +3666,9 @@ static const struct qcom_cc_desc gcc_ipq5332_desc = { 
	.num_resets = ARRAY_SIZE(gcc_ipq5332_resets),

	.clk_hws = gcc_ipq5332_hws,

	.num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),

	.icc_hws = icc_ipq5332_hws,

	.num_icc_hws = ARRAY_SIZE(icc_ipq5332_hws),

	.icc_first_node_id = IPQ_APPS_ID,

};



static int gcc_ipq5332_probe(struct platform_device *pdev)
@@ -3675,6 +3687,7 @@ static struct platform_driver gcc_ipq5332_driver = { 
	.driver = {

		.name = "gcc-ipq5332",

		.of_match_table = gcc_ipq5332_match_table,

		.sync_state = icc_sync_state,

	},

};