Commit 930293b7 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2025-02-20' of... 

Merge tag 'drm-intel-fixes-2025-02-20' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-fixes

- Use spin_lock_irqsave() in interruptible context on guc submission (Krzysztof)
- Fixes on DDI and TRANS programming (Imre)
- Make sure all planes in use by the joiner have their crtc included (Ville)
- Fix 128b/132b modeset issues (Imre)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Z7dgcUG_hvityvHn@intel.com
parents 619a1148 8058b49b

drivers/gpu/drm/i915/display/icl_dsi.c

+2 −2
Original line number Diff line number Diff line
@@ -809,8 +809,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 
		/* select data lane width */

		tmp = intel_de_read(display,

				    TRANS_DDI_FUNC_CTL(display, dsi_trans));

		tmp &= ~DDI_PORT_WIDTH_MASK;

		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);

		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;

		tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);



		/* select input pipe */

		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;

drivers/gpu/drm/i915/display/intel_ddi.c

+3 −5
Original line number Diff line number Diff line
@@ -658,7 +658,6 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state 
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);

	u32 ctl;



	if (DISPLAY_VER(dev_priv) >= 11)
@@ -678,8 +677,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state 
			 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);



	if (DISPLAY_VER(dev_priv) >= 12) {

		if (!intel_dp_mst_is_master_trans(crtc_state) ||

		    (!is_mst && intel_dp_is_uhbr(crtc_state))) {

		if (!intel_dp_mst_is_master_trans(crtc_state)) {

			ctl &= ~(TGL_TRANS_DDI_PORT_MASK |

				 TRANS_DDI_MODE_SELECT_MASK);

		}
@@ -3134,7 +3132,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 
	intel_dp_set_power(intel_dp, DP_SET_POWER_D3);



	if (DISPLAY_VER(dev_priv) >= 12) {

		if (is_mst) {

		if (is_mst || intel_dp_is_uhbr(old_crtc_state)) {

			enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;



			intel_de_rmw(dev_priv,
@@ -3487,7 +3485,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 
		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port),

			     XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);



		buf_ctl |= DDI_PORT_WIDTH(lane_count);

		buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);



		if (DISPLAY_VER(dev_priv) >= 20)

			buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;

drivers/gpu/drm/i915/display/intel_display.c

+18 −0
Original line number Diff line number Diff line
@@ -6628,12 +6628,30 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in 
static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)

{

	struct drm_i915_private *i915 = to_i915(state->base.dev);

	const struct intel_plane_state *plane_state;

	struct intel_crtc_state *crtc_state;

	struct intel_plane *plane;

	struct intel_crtc *crtc;

	u8 affected_pipes = 0;

	u8 modeset_pipes = 0;

	int i;



	/*

	 * Any plane which is in use by the joiner needs its crtc.

	 * Pull those in first as this will not have happened yet

	 * if the plane remains disabled according to uapi.

	 */

	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {

		crtc = to_intel_crtc(plane_state->hw.crtc);

		if (!crtc)

			continue;



		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);

		if (IS_ERR(crtc_state))

			return PTR_ERR(crtc_state);

	}



	/* Now pull in all joined crtcs */

	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {

		affected_pipes |= crtc_state->joiner_pipes;

		if (intel_crtc_needs_modeset(crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

+14 −1
Original line number Diff line number Diff line
@@ -1563,7 +1563,7 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp, 


	if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {

		lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");

		return false;

		goto out;

	}



	if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&
@@ -1575,6 +1575,19 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp, 
	       passed ? "passed" : "failed",

	       crtc_state->port_clock, crtc_state->lane_count);



out:

	/*

	 * Ensure that the training pattern does get set to TPS2 even in case

	 * of a failure, as is the case at the end of a passing link training

	 * and what is expected by the transcoder. Leaving TPS1 set (and

	 * disabling the link train mode in DP_TP_CTL later from TPS1 directly)

	 * would result in a stuck transcoder HW state and flip-done timeouts

	 * later in the modeset sequence.

	 */

	if (!passed)

		intel_dp_program_link_training_pattern(intel_dp, crtc_state,

						       DP_PHY_DPRX, DP_TRAINING_PATTERN_2);



	return passed;

}

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

+2 −2
Original line number Diff line number Diff line
@@ -3449,10 +3449,10 @@ static inline int guc_lrc_desc_unpin(struct intel_context *ce) 
	 */

	ret = deregister_context(ce, ce->guc_id.id);

	if (ret) {

		spin_lock(&ce->guc_state.lock);

		spin_lock_irqsave(&ce->guc_state.lock, flags);

		set_context_registered(ce);

		clr_context_destroyed(ce);

		spin_unlock(&ce->guc_state.lock);

		spin_unlock_irqrestore(&ce->guc_state.lock, flags);

		/*

		 * As gt-pm is awake at function entry, intel_wakeref_put_async merely decrements

		 * the wakeref immediately but per function spec usage call this after unlock.