Unverified Commit 93b63f68 authored by Qingfang Deng's avatar Qingfang Deng Committed by Palmer Dabbelt
Browse files

riscv: lib: relax assembly constraints in hweight 



rd and rs don't have to be the same. In some cases where rs needs to be
saved for later usage, this will save us some mv instructions.

Signed-off-by: default avatarQingfang Deng <qingfang.deng@siflower.com.cn>
Reviewed-by: default avatarXiao Wang <xiao.w.wang@intel.com>
Link: https://lore.kernel.org/r/20240527092405.134967-1-dqfext@gmail.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 6ad87359

arch/riscv/include/asm/arch_hweight.h

+4 −4
Original line number Diff line number Diff line
@@ -26,9 +26,9 @@ static __always_inline unsigned int __arch_hweight32(unsigned int w) 


	asm (".option push\n"

	     ".option arch,+zbb\n"

	     CPOPW "%0, %0\n"

	     CPOPW "%0, %1\n"

	     ".option pop\n"

	     : "+r" (w) : :);

	     : "=r" (w) : "r" (w) :);



	return w;
@@ -57,9 +57,9 @@ static __always_inline unsigned long __arch_hweight64(__u64 w) 


	asm (".option push\n"

	     ".option arch,+zbb\n"

	     "cpop %0, %0\n"

	     "cpop %0, %1\n"

	     ".option pop\n"

	     : "+r" (w) : :);

	     : "=r" (w) : "r" (w) :);



	return w;