Unverified Commit 93c06516 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

riscv: support for Svpbmt and D1 memory types 

Adds support for Svpbmt, the "Supervisor-mode: page-based memory types"
extension, which allows pages to be marked as non-cacheable and/or I/O.
This also includes support for the Allwinner D1's page table attributes
via the alternatives framework, which differ from Svpbmt in various ways
but are necessary to make the D1 function.

* palmer/riscv-d1:
  riscv: add memory-type errata for T-Head
  riscv: don't use global static vars to store alternative data
  riscv: remove FIXMAP_PAGE_IO and fall back to its default value
  riscv: add RISC-V Svpbmt extension support
  riscv: Fix accessing pfn bits in PTEs for non-32bit variants
  riscv: move boot alternatives to after fill_hwcap
  riscv: prevent compressed instructions in alternatives
  riscv: extend concatenated alternatives-lines to the same length
  riscv: implement ALTERNATIVE_2 macro
  riscv: implement module alternatives
  riscv: allow different stages with alternatives
  riscv: integrate alternatives better into the main architecture
parents d26eee72 a35707c3

arch/riscv/Kconfig

+28 −0
Original line number Diff line number Diff line
@@ -324,6 +324,21 @@ config NODES_SHIFT 
	  Specify the maximum number of NUMA Nodes available on the target

	  system.  Increases memory reserved to accommodate various tables.



config RISCV_ALTERNATIVE

	bool

	depends on !XIP_KERNEL

	help

	  This Kconfig allows the kernel to automatically patch the

	  errata required by the execution platform at run time. The

	  code patching is performed once in the boot stages. It means

	  that the overhead from this mechanism is just taken once.



config RISCV_ALTERNATIVE_EARLY

	bool

	depends on RISCV_ALTERNATIVE

	help

	  Allows early patching of the kernel for special errata



config RISCV_ISA_C

	bool "Emit compressed instructions when building Linux"

	default y
@@ -334,6 +349,19 @@ config RISCV_ISA_C 


	   If you don't know what to do here, say Y.



config RISCV_ISA_SVPBMT

	bool "SVPBMT extension support"

	depends on 64BIT && MMU

	select RISCV_ALTERNATIVE

	default y

	help

	   Adds support to dynamically detect the presence of the SVPBMT extension

	   (Supervisor-mode: page-based memory types) and enable its usage.



	   The SVPBMT extension is only available on 64Bit cpus.



	   If you don't know what to do here, say Y.



config FPU

	bool "FPU support"

	default y

arch/riscv/Kconfig.erratas

+23 −11
Original line number Diff line number Diff line 
menu "CPU errata selection"



config RISCV_ERRATA_ALTERNATIVE

	bool "RISC-V alternative scheme"

	depends on !XIP_KERNEL

	default y

	help

	  This Kconfig allows the kernel to automatically patch the

	  errata required by the execution platform at run time. The

	  code patching is performed once in the boot stages. It means

	  that the overhead from this mechanism is just taken once.



config ERRATA_SIFIVE

	bool "SiFive errata"

	depends on RISCV_ERRATA_ALTERNATIVE

	depends on !XIP_KERNEL

	select RISCV_ALTERNATIVE

	help

	  All SiFive errata Kconfig depend on this Kconfig. Disabling

	  this Kconfig will disable all SiFive errata. Please say "Y"
@@ -42,4 +33,25 @@ config ERRATA_SIFIVE_CIP_1200 


	  If you don't know what to do here, say "Y".



config ERRATA_THEAD

	bool "T-HEAD errata"

	select RISCV_ALTERNATIVE

	help

	  All T-HEAD errata Kconfig depend on this Kconfig. Disabling

	  this Kconfig will disable all T-HEAD errata. Please say "Y"

	  here if your platform uses T-HEAD CPU cores.



	  Otherwise, please say "N" here to avoid unnecessary overhead.



config ERRATA_THEAD_PBMT

	bool "Apply T-Head memory type errata"

	depends on ERRATA_THEAD && 64BIT

	select RISCV_ALTERNATIVE_EARLY

	default y

	help

	  This will apply the memory type errata to handle the non-standard

	  memory type bits in page-table-entries on T-Head SoCs.



	  If you don't know what to do here, say "Y".



endmenu

arch/riscv/Kconfig.socs

+0 −1
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ config SOC_SIFIVE 
	select CLK_SIFIVE

	select CLK_SIFIVE_PRCI

	select SIFIVE_PLIC

	select RISCV_ERRATA_ALTERNATIVE if !XIP_KERNEL

	select ERRATA_SIFIVE if !XIP_KERNEL

	help

	  This enables support for SiFive SoC platform hardware.

arch/riscv/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ endif 


head-y := arch/riscv/kernel/head.o



core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/

core-y += arch/riscv/errata/

core-$(CONFIG_KVM) += arch/riscv/kvm/



libs-y += arch/riscv/lib/

arch/riscv/errata/Makefile

+1 −1
Original line number Diff line number Diff line 
obj-y	+= alternative.o

obj-$(CONFIG_ERRATA_SIFIVE) += sifive/

obj-$(CONFIG_ERRATA_THEAD) += thead/