Commit 93cbc1ac authored by Haridhar Kalvala's avatar Haridhar Kalvala Committed by Matt Roper
Browse files

drm/i915/mtl: Add fake PCH for Meteor Lake 



Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.

On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC die in this case), unlike many past
platforms where the SDE was on a separate PCH die. The code is (badly)
structured today in a way that assumes the SDE is always on the PCH for
modern platforms, so on platforms where we don't actually need to identify
the PCH to figure out how the SDE behaves (i.e., all DG1/2 GPUs as well as
MTL and LNL),we've been assigning a "fake PCH" as a quickhack that allows
us to avoid restructuring a bunch of the code.we've been assigning a
"fake PCH" as a quick hack that allows us to avoid restructuring a bunch
of the code.

Removed unused macros of LNL amd MTL as well.

v2: Reorder PCH_MTL conditional check (Matt Roper)
    Reverting to PCH_MTL for PICA interrupt(Matt Roper)

Signed-off-by: default avatarHaridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231219185233.1469675-1-haridhar.kalvala@intel.com
parent e7b2d82d

drivers/gpu/drm/i915/display/intel_backlight.c

+1 −1
Original line number Diff line number Diff line
@@ -1465,7 +1465,7 @@ static bool cnp_backlight_controller_is_valid(struct drm_i915_private *i915, int 


	if (controller == 1 &&

	    INTEL_PCH_TYPE(i915) >= PCH_ICP &&

	    INTEL_PCH_TYPE(i915) < PCH_MTP)

	    INTEL_PCH_TYPE(i915) <= PCH_ADP)

		return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;



	return true;

drivers/gpu/drm/i915/display/intel_bios.c

+1 −2
Original line number Diff line number Diff line
@@ -2204,8 +2204,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) 
	if (IS_DGFX(i915))

		return vbt_pin;



	if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||

	    IS_ALDERLAKE_P(i915)) {

	if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {

		ddc_pin_map = adlp_ddc_pin_map;

		n_entries = ARRAY_SIZE(adlp_ddc_pin_map);

	} else if (IS_ALDERLAKE_S(i915)) {

drivers/gpu/drm/i915/display/intel_cdclk.c

+3 −3
Original line number Diff line number Diff line
@@ -3466,15 +3466,15 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) 
{

	u32 freq;



	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)

		freq = dg1_rawclk(dev_priv);

	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)

	if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)

		/*

		 * MTL always uses a 38.4 MHz rawclk.  The bspec tells us

		 * "RAWCLK_FREQ defaults to the values for 38.4 and does

		 * not need to be programmed."

		 */

		freq = 38400;

	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)

		freq = dg1_rawclk(dev_priv);

	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)

		freq = cnp_rawclk(dev_priv);

	else if (HAS_PCH_SPLIT(dev_priv))

drivers/gpu/drm/i915/display/intel_display_irq.c

+1 −1
Original line number Diff line number Diff line
@@ -986,7 +986,7 @@ static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_i 
	 * their flags both in the PICA and SDE IIR.

	 */

	if (*pch_iir & SDE_PICAINTERRUPT) {

		drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTP);

		drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTL);



		pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0);

		*pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR);

drivers/gpu/drm/i915/display/intel_gmbus.c

+1 −4
Original line number Diff line number Diff line
@@ -155,7 +155,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, 
	const struct gmbus_pin *pins;

	size_t size;



	if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {

	if (INTEL_PCH_TYPE(i915) >= PCH_MTL) {

		pins = gmbus_pins_mtp;

		size = ARRAY_SIZE(gmbus_pins_mtp);

	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
@@ -164,9 +164,6 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, 
	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {

		pins = gmbus_pins_dg1;

		size = ARRAY_SIZE(gmbus_pins_dg1);

	} else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {

		pins = gmbus_pins_mtp;

		size = ARRAY_SIZE(gmbus_pins_mtp);

	} else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {

		pins = gmbus_pins_icp;

		size = ARRAY_SIZE(gmbus_pins_icp);