Unverified Commit 95113bb7 authored by Yu Chien Peter Lin's avatar Yu Chien Peter Lin Committed by Palmer Dabbelt
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riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC 



The Andes hart-level interrupt controller (Andes INTC) allows AX45MP
cores to handle custom local interrupts, such as the performance
counter overflow interrupt.

Signed-off-by: default avatarYu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240222083946.3977135-6-peterlin@andestech.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent b88727d5

arch/riscv/boot/dts/renesas/r9a07g043f.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ cpu0: cpu@0 { 


			cpu0_intc: interrupt-controller {

				#interrupt-cells = <1>;

				compatible = "riscv,cpu-intc";

				compatible = "andestech,cpu-intc", "riscv,cpu-intc";

				interrupt-controller;

			};

		};