Commit 960609b2 authored by Ziyue Zhang's avatar Ziyue Zhang Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake GPIOs to PCIe port nodes... 


arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake GPIOs to PCIe port nodes and add port Nodes for all PCIe ports

Since describing the PCIe PHY directly under the RC node is now
deprecated, move the references to the respective PCIe port nodes,
creating them where necessary.Also add port nodes for PCIe5 and PCIe6a
with proper PHY references.

And also move the PCIe PERST and wake GPIOs from the controller nodes to
the corresponding PCIe port nodes on Hamoa-based platforms:

 - x1e001de-devkit
 - x1e78100-lenovo-thinkpad-t14s
 - x1e80100-asus-vivobook-s15
 - x1e80100-asus-zenbook-a14
 - x1e80100-dell-xps13-9345
 - x1e80100-lenovo-yoga-slim7x
 - x1e80100-microsoft-romulus
 - x1e80100-qcp

Signed-off-by: default avatarZiyue Zhang <ziyue.zhang@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260109104504.3147745-2-ziyue.zhang@oss.qualcomm.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 0e09a596

arch/arm64/boot/dts/qcom/hamoa.dtsi

+29 −13
Original line number Diff line number Diff line
@@ -3261,9 +3261,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 


			power-domains = <&gcc GCC_PCIE_3_GDSC>;



			phys = <&pcie3_phy>;

			phy-names = "pciephy";



			eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555

						     0x5555 0x5555 0x5555 0x5555>;

			eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
@@ -3404,12 +3401,14 @@ opp-128000000-4 { 
				};

			};



			pcie3_port: pcie@0 {

			pcie3_port0: pcie@0 {

				device_type = "pci";

				compatible = "pciclass,0604";

				reg = <0x0 0x0 0x0 0x0 0x0>;

				bus-range = <0x01 0xff>;



				phys = <&pcie3_phy>;



				#address-cells = <3>;

				#size-cells = <2>;

				ranges;
@@ -3538,13 +3537,22 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 
			power-domains = <&gcc GCC_PCIE_6A_GDSC>;

			required-opps = <&rpmhpd_opp_nom>;



			phys = <&pcie6a_phy>;

			phy-names = "pciephy";



			eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;

			eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;



			status = "disabled";



			pcie6a_port0: pcie@0 {

				device_type = "pci";

				reg = <0x0 0x0 0x0 0x0 0x0>;

				bus-range = <0x01 0xff>;



				phys = <&pcie6a_phy>;



				#address-cells = <3>;

				#size-cells = <2>;

				ranges;

			};

		};



		pcie6a_phy: phy@1bfc000 {
@@ -3670,12 +3678,21 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 
			power-domains = <&gcc GCC_PCIE_5_GDSC>;

			required-opps = <&rpmhpd_opp_nom>;



			phys = <&pcie5_phy>;

			phy-names = "pciephy";



			eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;



			status = "disabled";



			pcie5_port0: pcie@0 {

				device_type = "pci";

				reg = <0x0 0x0 0x0 0x0 0x0>;

				bus-range = <0x01 0xff>;



				phys = <&pcie5_phy>;



				#address-cells = <3>;

				#size-cells = <2>;

				ranges;

			};

		};



		pcie5_phy: phy@1c06000 {
@@ -3800,9 +3817,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 
			power-domains = <&gcc GCC_PCIE_4_GDSC>;

			required-opps = <&rpmhpd_opp_nom>;



			phys = <&pcie4_phy>;

			phy-names = "pciephy";



			eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;



			status = "disabled";
@@ -3812,6 +3826,8 @@ pcie4_port0: pcie@0 { 
				reg = <0x0 0x0 0x0 0x0 0x0>;

				bus-range = <0x01 0xff>;



				phys = <&pcie4_phy>;



				#address-cells = <3>;

				#size-cells = <2>;

				ranges;

arch/arm64/boot/dts/qcom/x1e001de-devkit.dts

+15 −9
Original line number Diff line number Diff line
@@ -1003,9 +1003,6 @@ &mdss_dp2_out { 
};



&pcie4 {

	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	pinctrl-0 = <&pcie4_default>;

	pinctrl-names = "default";
@@ -1019,10 +1016,12 @@ &pcie4_phy { 
	status = "okay";

};



&pcie5 {

	perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;

&pcie4_port0 {

	reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;

};



&pcie5 {

	vddpe-3v3-supply = <&vreg_wwan>;



	pinctrl-0 = <&pcie5_default>;
@@ -1038,10 +1037,12 @@ &pcie5_phy { 
	status = "okay";

};



&pcie6a {

	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;

&pcie5_port0 {

	reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;

};



&pcie6a {

	vddpe-3v3-supply = <&vreg_nvme>;



	pinctrl-names = "default";
@@ -1057,6 +1058,11 @@ &pcie6a_phy { 
	status = "okay";

};



&pcie6a_port0 {

	reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;

};



&pm8550_gpios {

	rtmr0_default: rtmr0-reset-n-active-state {

		pins = "gpio10";

arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi

+15 −9
Original line number Diff line number Diff line
@@ -1113,9 +1113,6 @@ &mdss_dp3_phy { 
};



&pcie4 {

	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	pinctrl-0 = <&pcie4_default>;

	pinctrl-names = "default";
@@ -1129,10 +1126,12 @@ &pcie4_phy { 
	status = "okay";

};



&pcie5 {

	perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;

&pcie4_port0 {

	reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;

};



&pcie5 {

	vddpe-3v3-supply = <&vreg_wwan>;



	pinctrl-0 = <&pcie5_default>;
@@ -1148,10 +1147,12 @@ &pcie5_phy { 
	status = "okay";

};



&pcie6a {

	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;

&pcie5_port0 {

	reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;

};



&pcie6a {

	vddpe-3v3-supply = <&vreg_nvme>;



	pinctrl-0 = <&pcie6a_default>;
@@ -1167,6 +1168,11 @@ &pcie6a_phy { 
	status = "okay";

};



&pcie6a_port0 {

	reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;

};



&pm8550_gpios {

	rtmr0_default: rtmr0-reset-n-active-state {

		pins = "gpio10";

arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts

+8 −6
Original line number Diff line number Diff line
@@ -907,9 +907,6 @@ &mdss_dp3_phy { 
};



&pcie4 {

	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	pinctrl-0 = <&pcie4_default>;

	pinctrl-names = "default";
@@ -924,6 +921,9 @@ &pcie4_phy { 
};



&pcie4_port0 {

	reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	wifi@0 {

		compatible = "pci17cb,1107";

		reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -941,9 +941,6 @@ wifi@0 { 
};



&pcie6a {

	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;



	vddpe-3v3-supply = <&vreg_nvme>;



	pinctrl-0 = <&pcie6a_default>;
@@ -959,6 +956,11 @@ &pcie6a_phy { 
	status = "okay";

};



&pcie6a_port0 {

	reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;

};



&pm8550_gpios {

	rtmr0_default: rtmr0-reset-n-active-state {

		pins = "gpio10";

arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts

+3 −0
Original line number Diff line number Diff line
@@ -82,6 +82,9 @@ &gpu_zap_shader { 
};



&pcie4_port0 {

	reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;

	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;



	wifi@0 {

		compatible = "pci17cb,1107";

		reg = <0x10000 0x0 0x0 0x0 0x0>;