Commit 96ac403e authored by mrigendrachaubey's avatar mrigendrachaubey Committed by Catalin Marinas
Browse files

arm64: Fix typos and spelling errors in comments 



This patch corrects several minor typographical and spelling errors
in comments across multiple arm64 source files.

No functional changes.

Signed-off-by: default avatarmrigendrachaubey <mrigendra.chaubey@gmail.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 3a866087

arch/arm64/include/asm/assembler.h

+2 −2
Original line number Diff line number Diff line
@@ -371,7 +371,7 @@ alternative_endif 
 * [start, end) with dcache line size explicitly provided.

 *

 * 	op:		operation passed to dc instruction

 * 	domain:		domain used in dsb instruciton

 * 	domain:		domain used in dsb instruction

 * 	start:          starting virtual address of the region

 * 	end:            end virtual address of the region

 *	linesz:		dcache line size
@@ -412,7 +412,7 @@ alternative_endif 
 * [start, end)

 *

 * 	op:		operation passed to dc instruction

 * 	domain:		domain used in dsb instruciton

 * 	domain:		domain used in dsb instruction

 * 	start:          starting virtual address of the region

 * 	end:            end virtual address of the region

 * 	fixup:		optional label to branch to on user fault

arch/arm64/include/asm/cpufeature.h

+2 −2
Original line number Diff line number Diff line
@@ -199,7 +199,7 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; 
 *    registers (e.g, SCTLR, TCR etc.) or patching the kernel via

 *    alternatives. The kernel patching is batched and performed at later

 *    point. The actions are always initiated only after the capability

 *    is finalised. This is usally denoted by "enabling" the capability.

 *    is finalised. This is usually denoted by "enabling" the capability.

 *    The actions are initiated as follows :

 *	a) Action is triggered on all online CPUs, after the capability is

 *	finalised, invoked within the stop_machine() context from
@@ -251,7 +251,7 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; 
#define ARM64_CPUCAP_SCOPE_LOCAL_CPU		((u16)BIT(0))

#define ARM64_CPUCAP_SCOPE_SYSTEM		((u16)BIT(1))

/*

 * The capabilitiy is detected on the Boot CPU and is used by kernel

 * The capability is detected on the Boot CPU and is used by kernel

 * during early boot. i.e, the capability should be "detected" and

 * "enabled" as early as possibly on all booting CPUs.

 */

arch/arm64/include/asm/el2_setup.h

+1 −1
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ 
	 * Fruity CPUs seem to have HCR_EL2.E2H set to RAO/WI, but

	 * don't advertise it (they predate this relaxation).

	 *

	 * Initalize HCR_EL2.E2H so that later code can rely upon HCR_EL2.E2H

	 * Initialize HCR_EL2.E2H so that later code can rely upon HCR_EL2.E2H

	 * indicating whether the CPU is running in E2H mode.

	 */

	mrs_s	x1, SYS_ID_AA64MMFR4_EL1

arch/arm64/include/asm/pgtable.h

+2 −2
Original line number Diff line number Diff line
@@ -432,7 +432,7 @@ bool pgattr_change_is_safe(pteval_t old, pteval_t new); 
 *   1      0      |   1           0          1

 *   1      1      |   0           1          x

 *

 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via

 * When hardware DBM is not present, the software PTE_DIRTY bit is updated via

 * the page fault mechanism. Checking the dirty status of a pte becomes:

 *

 *   PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
@@ -598,7 +598,7 @@ static inline int pte_protnone(pte_t pte) 
	/*

	 * pte_present_invalid() tells us that the pte is invalid from HW

	 * perspective but present from SW perspective, so the fields are to be

	 * interpretted as per the HW layout. The second 2 checks are the unique

	 * interpreted as per the HW layout. The second 2 checks are the unique

	 * encoding that we use for PROT_NONE. It is insufficient to only use

	 * the first check because we share the same encoding scheme with pmds

	 * which support pmd_mkinvalid(), so can be present-invalid without

arch/arm64/include/asm/suspend.h

+1 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ struct cpu_suspend_ctx { 
 * __cpu_suspend_enter()'s caller, and populated by __cpu_suspend_enter().

 * This data must survive until cpu_resume() is called.

 *

 * This struct desribes the size and the layout of the saved cpu state.

 * This struct describes the size and the layout of the saved cpu state.

 * The layout of the callee_saved_regs is defined by the implementation

 * of __cpu_suspend_enter(), and cpu_resume(). This struct must be passed

 * in by the caller as __cpu_suspend_enter()'s stack-frame is gone once it