Commit 96c420d5 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Use a plain old int for the cdclk/mdclk ratio 



No point in throwing around u8 when we're dealing with
just an integer. Use a plain old boring 'int'.

Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240402155016.13733-14-ville.syrjala@linux.intel.com
parent 8c5dbb50

drivers/gpu/drm/i915/display/intel_cdclk.c

+3 −3
Original line number Diff line number Diff line
@@ -1893,7 +1893,7 @@ static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915) 
	return MDCLK_SOURCE_SEL_CD2XCLK;

}



u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,

int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,

			    const struct intel_cdclk_config *cdclk_config)

{

	if (mdclk_source_is_cdclk_pll(i915))
@@ -3333,7 +3333,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 


	if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) !=

	    intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) {

		u8 ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual);

		int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual);



		ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);

		if (ret)

drivers/gpu/drm/i915/display/intel_cdclk.h

+2 −2
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv); 
u32 intel_read_rawclk(struct drm_i915_private *dev_priv);

bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,

			       const struct intel_cdclk_config *b);

u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,

int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,

			    const struct intel_cdclk_config *cdclk_config);

bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);

void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);

drivers/gpu/drm/i915/display/skl_watermark.c

+4 −2
Original line number Diff line number Diff line
@@ -3616,7 +3616,8 @@ static void intel_mbus_dbox_update(struct intel_atomic_state *state) 
	}

}



int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 ratio)

int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,

					   int ratio)

{

	struct intel_dbuf_state *dbuf_state;
@@ -3629,7 +3630,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 
	return intel_atomic_lock_global_state(&dbuf_state->base);

}



void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus)

void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,

					 int ratio, bool joined_mbus)

{

	enum dbuf_slice slice;

drivers/gpu/drm/i915/display/skl_watermark.h

+4 −2
Original line number Diff line number Diff line
@@ -74,11 +74,13 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state); 
	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))



int intel_dbuf_init(struct drm_i915_private *i915);

int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 ratio);

int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,

					   int ratio);



void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);

void intel_dbuf_post_plane_update(struct intel_atomic_state *state);

void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus);

void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,

					 int ratio, bool joined_mbus);

void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);

void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);