Commit 9776dd36 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-irq-2024-05-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 interrupt handling updates from Thomas Gleixner:
 "Add support for posted interrupts on bare metal.

  Posted interrupts is a virtualization feature which allows to inject
  interrupts directly into a guest without host interaction. The VT-d
  interrupt remapping hardware sets the bit which corresponds to the
  interrupt vector in a vector bitmap which is either used to inject the
  interrupt directly into the guest via a virtualized APIC or in case
  that the guest is scheduled out provides a host side notification
  interrupt which informs the host that an interrupt has been marked
  pending in the bitmap.

  This can be utilized on bare metal for scenarios where multiple
  devices, e.g. NVME storage, raise interrupts with a high frequency. In
  the default mode these interrupts are handles independently and
  therefore require a full roundtrip of interrupt entry/exit.

  Utilizing posted interrupts this roundtrip overhead can be avoided by
  coalescing these interrupt entries to a single entry for the posted
  interrupt notification. The notification interrupt then demultiplexes
  the pending bits in a memory based bitmap and invokes the
  corresponding device specific handlers.

  Depending on the usage scenario and device utilization throughput
  improvements between 10% and 130% have been measured.

  As this is only relevant for high end servers with multiple device
  queues per CPU attached and counterproductive for situations where
  interrupts are arriving at distinct times, the functionality is opt-in
  via a kernel command line parameter"

* tag 'x86-irq-2024-05-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/irq: Use existing helper for pending vector check
  iommu/vt-d: Enable posted mode for device MSIs
  iommu/vt-d: Make posted MSI an opt-in command line option
  x86/irq: Extend checks for pending vectors to posted interrupts
  x86/irq: Factor out common code for checking pending interrupts
  x86/irq: Install posted MSI notification handler
  x86/irq: Factor out handler invocation from common_interrupt()
  x86/irq: Set up per host CPU posted interrupt descriptors
  x86/irq: Reserve a per CPU IDT vector for posted MSIs
  x86/irq: Add a Kconfig option for posted MSI
  x86/irq: Remove bitfields in posted interrupt descriptor
  x86/irq: Unionize PID.PIR for 64bit access w/o casting
  KVM: VMX: Move posted interrupt descriptor out of VMX code
parents 6bfd2d44 6ecc2e79

Documentation/admin-guide/kernel-parameters.txt

+2 −0
Original line number Diff line number Diff line
@@ -2251,6 +2251,8 @@ 
			no_x2apic_optout

				BIOS x2APIC opt-out request will be ignored

			nopost	disable Interrupt Posting

			posted_msi

				enable MSIs delivered as posted interrupts



	iomem=		Disable strict checking of access to MMIO memory

		strict	regions from userspace.

arch/x86/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -466,6 +466,17 @@ config X86_X2APIC 


	  If you don't know what to do here, say N.



config X86_POSTED_MSI

	bool "Enable MSI and MSI-x delivery by posted interrupts"

	depends on X86_64 && IRQ_REMAP

	help

	  This enables MSIs that are under interrupt remapping to be delivered as

	  posted interrupts to the host kernel. Interrupt throughput can

	  potentially be improved by coalescing CPU notifications during high

	  frequency bursts.



	  If you don't know what to do here, say N.



config X86_MPPARSE

	bool "Enable MPS table" if ACPI

	default y

arch/x86/entry/entry_fred.c

+2 −0
Original line number Diff line number Diff line
@@ -117,6 +117,8 @@ static idtentry_t sysvec_table[NR_SYSTEM_VECTORS] __ro_after_init = { 
	SYSVEC(POSTED_INTR_VECTOR,		kvm_posted_intr_ipi),

	SYSVEC(POSTED_INTR_WAKEUP_VECTOR,	kvm_posted_intr_wakeup_ipi),

	SYSVEC(POSTED_INTR_NESTED_VECTOR,	kvm_posted_intr_nested_ipi),



	SYSVEC(POSTED_MSI_NOTIFICATION_VECTOR,	posted_msi_notification),

};



static bool fred_setup_done __initdata;

arch/x86/include/asm/apic.h

+6 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <asm/msr.h>

#include <asm/hardirq.h>

#include <asm/io.h>

#include <asm/posted_intr.h>



#define ARCH_APICTIMER_STOPS_ON_C3	1
@@ -500,6 +501,11 @@ static inline bool lapic_vector_set_in_irr(unsigned int vector) 
	return !!(irr & (1U << (vector % 32)));

}



static inline bool is_vector_pending(unsigned int vector)

{

	return lapic_vector_set_in_irr(vector) || pi_pending_this_cpu(vector);

}



/*

 * Warm reset vector position:

 */

arch/x86/include/asm/hardirq.h

+6 −0
Original line number Diff line number Diff line
@@ -44,10 +44,16 @@ typedef struct { 
	unsigned int irq_hv_reenlightenment_count;

	unsigned int hyperv_stimer0_count;

#endif

#ifdef CONFIG_X86_POSTED_MSI

	unsigned int posted_msi_notification_count;

#endif

} ____cacheline_aligned irq_cpustat_t;



DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);



#ifdef CONFIG_X86_POSTED_MSI

DECLARE_PER_CPU_ALIGNED(struct pi_desc, posted_msi_pi_desc);

#endif

#define __ARCH_IRQ_STAT



#define inc_irq_stat(member)	this_cpu_inc(irq_stat.member)