Commit 9807aba1 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/cdclk: make struct intel_cdclk_state opaque 



With all the code touching struct intel_cdclk_state moved inside
intel_cdclk.c, we move the struct definition there too, and make the
type opaque. This nicely reduces includes from intel_cdclk.h.

Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/2b58c52e8cbcb66a48ecd4a1453e49dc7bd66289.1750847509.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 79be2da5

drivers/gpu/drm/i915/display/intel_cdclk.c

+36 −0
Original line number Diff line number Diff line
@@ -114,6 +114,42 @@ 
 * dividers can be programmed correctly.

 */



struct intel_cdclk_state {

	struct intel_global_state base;



	/*

	 * Logical configuration of cdclk (used for all scaling,

	 * watermark, etc. calculations and checks). This is

	 * computed as if all enabled crtcs were active.

	 */

	struct intel_cdclk_config logical;



	/*

	 * Actual configuration of cdclk, can be different from the

	 * logical configuration only when all crtc's are DPMS off.

	 */

	struct intel_cdclk_config actual;



	/* minimum acceptable cdclk to satisfy bandwidth requirements */

	int bw_min_cdclk;

	/* minimum acceptable cdclk for each pipe */

	int min_cdclk[I915_MAX_PIPES];

	/* minimum acceptable voltage level for each pipe */

	u8 min_voltage_level[I915_MAX_PIPES];



	/* pipe to which cd2x update is synchronized */

	enum pipe pipe;



	/* forced minimum cdclk for glk+ audio w/a */

	int force_min_cdclk;



	/* bitmask of active pipes */

	u8 active_pipes;



	/* update cdclk with pipes disabled */

	bool disable_pipes;

};



struct intel_cdclk_funcs {

	void (*get_cdclk)(struct intel_display *display,

			  struct intel_cdclk_config *cdclk_config);

drivers/gpu/drm/i915/display/intel_cdclk.h

+2 −39
Original line number Diff line number Diff line
@@ -8,10 +8,9 @@ 


#include <linux/types.h>



#include "intel_display_limits.h"

#include "intel_global_state.h"



enum pipe;

struct intel_atomic_state;

struct intel_cdclk_state;

struct intel_crtc;

struct intel_crtc_state;

struct intel_display;
@@ -23,42 +22,6 @@ struct intel_cdclk_config { 
	bool joined_mbus;

};



struct intel_cdclk_state {

	struct intel_global_state base;



	/*

	 * Logical configuration of cdclk (used for all scaling,

	 * watermark, etc. calculations and checks). This is

	 * computed as if all enabled crtcs were active.

	 */

	struct intel_cdclk_config logical;



	/*

	 * Actual configuration of cdclk, can be different from the

	 * logical configuration only when all crtc's are DPMS off.

	 */

	struct intel_cdclk_config actual;



	/* minimum acceptable cdclk to satisfy bandwidth requirements */

	int bw_min_cdclk;

	/* minimum acceptable cdclk for each pipe */

	int min_cdclk[I915_MAX_PIPES];

	/* minimum acceptable voltage level for each pipe */

	u8 min_voltage_level[I915_MAX_PIPES];



	/* pipe to which cd2x update is synchronized */

	enum pipe pipe;



	/* forced minimum cdclk for glk+ audio w/a */

	int force_min_cdclk;



	/* bitmask of active pipes */

	u8 active_pipes;



	/* update cdclk with pipes disabled */

	bool disable_pipes;

};



void intel_cdclk_init_hw(struct intel_display *display);

void intel_cdclk_uninit_hw(struct intel_display *display);

void intel_init_cdclk_hooks(struct intel_display *display);