Commit 981724b4 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.14-2025-02-13' of... 

Merge tag 'amd-drm-fixes-6.14-2025-02-13' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.14-2025-02-13:

amdgpu:
- Fix shutdown regression on old APUs
- Fix compute queue hang on gfx9 APUs
- Fix possible invalid access in PSP failure path
- Avoid possible buffer overflow in pptable override

amdkfd:
- Properly free gang bo in failure path
- GFX12 trap handler fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213153843.242640-1-alexander.deucher@amd.com
parents 79f9efa0 1abb2648

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -120,9 +120,10 @@ 
 * - 3.58.0 - Add GFX12 DCC support

 * - 3.59.0 - Cleared VRAM

 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)

 * - 3.61.0 - Contains fix for RV/PCO compute queues

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	60

#define KMS_DRIVER_MINOR	61

#define KMS_DRIVER_PATCHLEVEL	0



/*

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+3 −2
Original line number Diff line number Diff line
@@ -3815,10 +3815,11 @@ int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 
		if (err == -ENODEV) {

			dev_warn(adev->dev, "cap microcode does not exist, skip\n");

			err = 0;

			goto out;

		}

		} else {

			dev_err(adev->dev, "fail to initialize cap microcode\n");

		}

		goto out;

	}



	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];

	info->ucode_id = AMDGPU_UCODE_ID_CAP;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+34 −2
Original line number Diff line number Diff line
@@ -7437,6 +7437,38 @@ static void gfx_v9_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */

}



static void gfx_v9_0_ring_begin_use_compute(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	struct amdgpu_ip_block *gfx_block =

		amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);



	amdgpu_gfx_enforce_isolation_ring_begin_use(ring);



	/* Raven and PCO APUs seem to have stability issues

	 * with compute and gfxoff and gfx pg.  Disable gfx pg during

	 * submission and allow again afterwards.

	 */

	if (gfx_block && amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 1, 0))

		gfx_v9_0_set_powergating_state(gfx_block, AMD_PG_STATE_UNGATE);

}



static void gfx_v9_0_ring_end_use_compute(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	struct amdgpu_ip_block *gfx_block =

		amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);



	/* Raven and PCO APUs seem to have stability issues

	 * with compute and gfxoff and gfx pg.  Disable gfx pg during

	 * submission and allow again afterwards.

	 */

	if (gfx_block && amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 1, 0))

		gfx_v9_0_set_powergating_state(gfx_block, AMD_PG_STATE_GATE);



	amdgpu_gfx_enforce_isolation_ring_end_use(ring);

}



static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {

	.name = "gfx_v9_0",

	.early_init = gfx_v9_0_early_init,
@@ -7613,8 +7645,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 
	.emit_wave_limit = gfx_v9_0_emit_wave_limit,

	.reset = gfx_v9_0_reset_kcq,

	.emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader,

	.begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,

	.end_use = amdgpu_gfx_enforce_isolation_ring_end_use,

	.begin_use = gfx_v9_0_ring_begin_use_compute,

	.end_use = gfx_v9_0_ring_end_use_compute,

};



static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h

+2 −1
Original line number Diff line number Diff line
@@ -4121,7 +4121,8 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 
	0x0000ffff, 0x8bfe7e7e,

	0x8bea6a6a, 0xb97af804,

	0xbe804ec2, 0xbf94fffe,

	0xbe804a6c, 0xbfb10000,

	0xbe804a6c, 0xbe804ec2,

	0xbf94fffe, 0xbfb10000,

	0xbf9f0000, 0xbf9f0000,

	0xbf9f0000, 0xbf9f0000,

	0xbf9f0000, 0x00000000,

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm

+4 −0
Original line number Diff line number Diff line
@@ -1049,6 +1049,10 @@ L_SKIP_BARRIER_RESTORE: 
	s_rfe_b64	s_restore_pc_lo						//Return to the main shader program and resume execution



L_END_PGM:

	// Make sure that no wave of the workgroup can exit the trap handler

	// before the workgroup barrier state is saved.

	s_barrier_signal	-2

	s_barrier_wait	-2

	s_endpgm_saved

end