Loading arch/arm64/kvm/hyp.S +22 −0 Original line number Diff line number Diff line Loading @@ -1030,6 +1030,28 @@ ENTRY(__kvm_tlb_flush_vmid_ipa) ret ENDPROC(__kvm_tlb_flush_vmid_ipa) /** * void __kvm_tlb_flush_vmid(struct kvm *kvm) - Flush per-VMID TLBs * @struct kvm *kvm - pointer to kvm structure * * Invalidates all Stage 1 and 2 TLB entries for current VMID. */ ENTRY(__kvm_tlb_flush_vmid) dsb ishst kern_hyp_va x0 ldr x2, [x0, #KVM_VTTBR] msr vttbr_el2, x2 isb tlbi vmalls12e1is dsb ish isb msr vttbr_el2, xzr ret ENDPROC(__kvm_tlb_flush_vmid) ENTRY(__kvm_flush_vm_context) dsb ishst tlbi alle1is Loading Loading
arch/arm64/kvm/hyp.S +22 −0 Original line number Diff line number Diff line Loading @@ -1030,6 +1030,28 @@ ENTRY(__kvm_tlb_flush_vmid_ipa) ret ENDPROC(__kvm_tlb_flush_vmid_ipa) /** * void __kvm_tlb_flush_vmid(struct kvm *kvm) - Flush per-VMID TLBs * @struct kvm *kvm - pointer to kvm structure * * Invalidates all Stage 1 and 2 TLB entries for current VMID. */ ENTRY(__kvm_tlb_flush_vmid) dsb ishst kern_hyp_va x0 ldr x2, [x0, #KVM_VTTBR] msr vttbr_el2, x2 isb tlbi vmalls12e1is dsb ish isb msr vttbr_el2, xzr ret ENDPROC(__kvm_tlb_flush_vmid) ENTRY(__kvm_flush_vm_context) dsb ishst tlbi alle1is Loading