Commit 9850a1c4 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: add dwb support to dml2 



[why]
dwb was not POR previosly.
now need to enable dwb in dml2.

Limitation:
HW DML assumes only one DWB
one set of watermark for all 4 watermark sets
one stream has one DWB only.
WB scaling dml input has one set of scaling tap.
(no chroma so far)

needs to follow up

Reviewed-by: default avatarChris Park <chris.park@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ded99dac

drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c

+1 −0
Original line number Diff line number Diff line
@@ -10214,6 +10214,7 @@ dml_get_var_func(fraction_of_urgent_bandwidth_imm_flip, dml_float_t, mode_lib->m 
dml_get_var_func(urgent_latency, dml_float_t, mode_lib->mp.UrgentLatency);

dml_get_var_func(clk_dcf_deepsleep, dml_float_t, mode_lib->mp.DCFCLKDeepSleep);

dml_get_var_func(wm_writeback_dram_clock_change, dml_float_t, mode_lib->mp.Watermark.WritebackDRAMClockChangeWatermark);

dml_get_var_func(wm_writeback_urgent, dml_float_t, mode_lib->mp.Watermark.WritebackUrgentWatermark);

dml_get_var_func(stutter_efficiency, dml_float_t, mode_lib->mp.StutterEfficiency);

dml_get_var_func(stutter_efficiency_no_vblank, dml_float_t, mode_lib->mp.StutterEfficiencyNotIncludingVBlank);

dml_get_var_func(stutter_efficiency_z8, dml_float_t, mode_lib->mp.Z8StutterEfficiency);

drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h

+1 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ dml_get_var_decl(wm_usr_retraining, dml_float_t); 
dml_get_var_decl(urgent_latency, dml_float_t);



dml_get_var_decl(wm_writeback_dram_clock_change, dml_float_t);

dml_get_var_decl(wm_writeback_urgent, dml_float_t);

dml_get_var_decl(stutter_efficiency_no_vblank, dml_float_t);

dml_get_var_decl(stutter_efficiency, dml_float_t);

dml_get_var_decl(stutter_efficiency_z8, dml_float_t);

drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h

+2 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ 
#define DCN_DML__VM_PRESENT__1 1

#define DCN_DML__HOST_VM_PRESENT 1

#define DCN_DML__HOST_VM_PRESENT__1 1

#define DCN_DML__DWB 1



#include "dml_depedencies.h"
@@ -59,6 +60,7 @@ 
#define __DML_NUM_PLANES__                              DCN_DML__NUM_PLANE

#define __DML_NUM_CURSORS__                             DCN_DML__NUM_CURSOR

#define __DML_DPP_INVALID__                             0

#define __DML_NUM_DMB__                                 DCN_DML__DWB

#define __DML_PIPE_NO_PLANE__                           99



#define __DML_MAX_STATE_ARRAY_SIZE__        DCN_DML__NUM_PWR_STATE

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c

+44 −1
Original line number Diff line number Diff line
@@ -1061,7 +1061,46 @@ static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2, 
		plane_index = 0;

	}

}



static void populate_dml_writeback_cfg_from_stream_state(struct dml_writeback_cfg_st *out,

		unsigned int location, const struct dc_stream_state *in)

{

	if (in->num_wb_info > 0) {

		for (int i = 0; i < __DML_NUM_DMB__; i++) {

			const struct dc_writeback_info *wb_info = &in->writeback_info[i];

			/*current dml support 1 dwb per stream, limitation*/

			if (wb_info->wb_enabled) {

				out->WritebackEnable[location] = wb_info->wb_enabled;

				out->ActiveWritebacksPerSurface[location] = wb_info->dwb_params.cnv_params.src_width;

				out->WritebackDestinationWidth[location] = wb_info->dwb_params.dest_width;

				out->WritebackDestinationHeight[location] = wb_info->dwb_params.dest_height;



				out->WritebackSourceWidth[location] = wb_info->dwb_params.cnv_params.crop_en ?

					wb_info->dwb_params.cnv_params.crop_width :

					wb_info->dwb_params.cnv_params.src_width;



				out->WritebackSourceHeight[location] = wb_info->dwb_params.cnv_params.crop_en ?

					wb_info->dwb_params.cnv_params.crop_height :

					wb_info->dwb_params.cnv_params.src_height;

				/*current design does not have chroma scaling, need to follow up*/

				out->WritebackHTaps[location] = wb_info->dwb_params.scaler_taps.h_taps > 0 ?

					wb_info->dwb_params.scaler_taps.h_taps : 1;

				out->WritebackVTaps[location] = wb_info->dwb_params.scaler_taps.v_taps > 0 ?

					wb_info->dwb_params.scaler_taps.v_taps : 1;



				out->WritebackHRatio[location] = wb_info->dwb_params.cnv_params.crop_en ?

					(double)wb_info->dwb_params.cnv_params.crop_width /

						(double)wb_info->dwb_params.dest_width :

					(double)wb_info->dwb_params.cnv_params.src_width /

						(double)wb_info->dwb_params.dest_width;

				out->WritebackVRatio[location] = wb_info->dwb_params.cnv_params.crop_en ?

					(double)wb_info->dwb_params.cnv_params.crop_height /

						(double)wb_info->dwb_params.dest_height :

					(double)wb_info->dwb_params.cnv_params.src_height /

						(double)wb_info->dwb_params.dest_height;

			}

		}

	}

}

void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg)

{

	int i = 0, j = 0, k = 0;
@@ -1106,6 +1145,10 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat 


		populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]);

		populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context);

		/*Call site for populate_dml_writeback_cfg_from_stream_state*/

		populate_dml_writeback_cfg_from_stream_state(&dml_dispcfg->writeback,

			disp_cfg_stream_location, context->streams[i]);



		switch (context->streams[i]->debug.force_odm_combine_segments) {

		case 2:

			dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_2to1;

drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c

+65 −0
Original line number Diff line number Diff line
@@ -404,6 +404,71 @@ void dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display 
	watermark->cstate_pstate.cstate_exit_z8_ns = dml_get_wm_z8_stutter(dml_core_ctx) * 1000;

}



unsigned int dml2_calc_max_scaled_time(

		unsigned int time_per_pixel,

		enum mmhubbub_wbif_mode mode,

		unsigned int urgent_watermark)

{

	unsigned int time_per_byte = 0;

	unsigned int total_free_entry = 0xb40;

	unsigned int buf_lh_capability;

	unsigned int max_scaled_time;



	if (mode == PACKED_444) /* packed mode 32 bpp */

		time_per_byte = time_per_pixel/4;

	else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */

		time_per_byte = time_per_pixel/8;



	if (time_per_byte == 0)

		time_per_byte = 1;



	buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/

	max_scaled_time   = buf_lh_capability - urgent_watermark;

	return max_scaled_time;

}



void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib_st *dml_core_ctx)

{

	int i, j = 0;;

	struct mcif_arb_params *wb_arb_params = NULL;

	struct dcn_bw_writeback *bw_writeback = NULL;

	enum mmhubbub_wbif_mode wbif_mode = PACKED_444_FP16; /*for now*/



	if (context->stream_count != 0) {

		for (i = 0; i < context->stream_count; i++) {

			if (context->streams[i]->num_wb_info != 0)

				j++;

		}

	}

	if (j == 0) /*no dwb */

		return;

	for (i = 0; i < __DML_NUM_DMB__; i++) {

		bw_writeback = &context->bw_ctx.bw.dcn.bw_writeback;

		wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[i];



		for (j = 0 ; j < 4; j++) {

			/*current dml only has one set of watermark, need to follow up*/

			bw_writeback->mcif_wb_arb[i].cli_watermark[j] =

					dml_get_wm_writeback_urgent(dml_core_ctx) * 1000;

			bw_writeback->mcif_wb_arb[i].pstate_watermark[j] =

					dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000;

		}

		if (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk != 0) {

			/* time_per_pixel should be in u6.6 format */

			bw_writeback->mcif_wb_arb[i].time_per_pixel =

				(1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;

		}

		bw_writeback->mcif_wb_arb[i].slice_lines = 32;

		bw_writeback->mcif_wb_arb[i].arbitration_slice = 2;

		bw_writeback->mcif_wb_arb[i].max_scaled_time =

			dml2_calc_max_scaled_time(wb_arb_params->time_per_pixel,

					wbif_mode, 	wb_arb_params->cli_watermark[0]);

		/*not required any more*/

		bw_writeback->mcif_wb_arb[i].dram_speed_change_duration =

			dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000;



	}

}

void dml2_initialize_det_scratch(struct dml2_context *in_ctx)

{

	int i;