Commit 9977754e authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC 



Add the initial DTSI for the RZ/G3E SoC.
The files in this commit have the following meaning:
  - r9a09g047.dtsi:    RZ/G3E family SoC common parts
  - r9a09g047e57.dtsi: RZ/G3E R0A09G047E{4,5}{7,8} SoC specific parts
  - r9a09g047e37.dtsi: RZ/G3E R0A09G047E{2,3}{7,8} SoC specific parts

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-10-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 6977c89b

arch/arm64/boot/dts/renesas/r9a09g047.dtsi

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

/*

 * Device Tree Source for the RZ/G3E SoC

 *

 * Copyright (C) 2024 Renesas Electronics Corp.

 */



#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	compatible = "renesas,r9a09g047";

	#address-cells = <2>;

	#size-cells = <2>;



	audio_extal_clk: audio-clk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board */

		clock-frequency = <0>;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			compatible = "arm,cortex-a55";

			reg = <0>;

			device_type = "cpu";

			next-level-cache = <&L3_CA55>;

			enable-method = "psci";

		};



		cpu1: cpu@100 {

			compatible = "arm,cortex-a55";

			reg = <0x100>;

			device_type = "cpu";

			next-level-cache = <&L3_CA55>;

			enable-method = "psci";

		};



		cpu2: cpu@200 {

			compatible = "arm,cortex-a55";

			reg = <0x200>;

			device_type = "cpu";

			next-level-cache = <&L3_CA55>;

			enable-method = "psci";

		};



		cpu3: cpu@300 {

			compatible = "arm,cortex-a55";

			reg = <0x300>;

			device_type = "cpu";

			next-level-cache = <&L3_CA55>;

			enable-method = "psci";

		};



		L3_CA55: cache-controller-0 {

			compatible = "cache";

			cache-unified;

			cache-size = <0x100000>;

			cache-level = <3>;

		};

	};



	psci {

		compatible = "arm,psci-1.0", "arm,psci-0.2";

		method = "smc";

	};



	qextal_clk: qextal-clk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board */

		clock-frequency = <0>;

	};



	rtxin_clk: rtxin-clk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board */

		clock-frequency = <0>;

	};



	soc: soc {

		compatible = "simple-bus";

		interrupt-parent = <&gic>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		cpg: clock-controller@10420000 {

			compatible = "renesas,r9a09g047-cpg";

			reg = <0 0x10420000 0 0x10000>;

			clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;

			clock-names = "audio_extal", "rtxin", "qextal";

			#clock-cells = <2>;

			#reset-cells = <1>;

			#power-domain-cells = <0>;

		};



		scif0: serial@11c01400 {

			compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057";

			reg = <0 0x11c01400 0 0x400>;

			interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "eri", "rxi", "txi", "bri", "dri",

					  "tei", "tei-dri", "rxi-edge", "txi-edge";

			clocks = <&cpg CPG_MOD 0x8f>;

			clock-names = "fck";

			power-domains = <&cpg>;

			resets = <&cpg 0x95>;

			status = "disabled";

		};



		gic: interrupt-controller@14900000 {

			compatible = "arm,gic-v3";

			reg = <0x0 0x14900000 0 0x20000>,

			      <0x0 0x14940000 0 0x80000>;

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,

				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;

		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";

	};

};

arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

/*

 * Device Tree Source for the RZ/G3E R9A09G047E37 SoC specific parts

 *

 * Copyright (C) 2024 Renesas Electronics Corp.

 */



/dts-v1/;

#include "r9a09g047.dtsi"



/ {

	compatible = "renesas,r9a09g047e37", "renesas,r9a09g047";



	cpus {

		/delete-node/ cpu@200;

		/delete-node/ cpu@300;

	};

};

arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

/*

 * Device Tree Source for the RZ/G3E R9A09G047E57 SoC specific parts

 *

 * Copyright (C) 2024 Renesas Electronics Corp.

 */



/dts-v1/;

#include "r9a09g047.dtsi"



/ {

	compatible = "renesas,r9a09g047e57", "renesas,r9a09g047";

};