Commit 99905815 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: move icl_sagv_{pre, post}_plane_update() to intel_bw.c 



Prefer only looking at struct intel_bw_state internals inside
intel_bw.c. To that effect, move icl_sagv_{pre,post}_plane_update()
there.

Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/dedcbeb3389ecd50195aa37de75e9992fae5d197.1750847509.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 4822cb81

drivers/gpu/drm/i915/display/intel_bw.c

+66 −2
Original line number Diff line number Diff line
@@ -153,7 +153,7 @@ static bool is_sagv_enabled(struct intel_display *display, u16 points_mask) 
			      ICL_PCODE_REQ_QGV_PT_MASK);

}



int icl_pcode_restrict_qgv_points(struct intel_display *display,

static int icl_pcode_restrict_qgv_points(struct intel_display *display,

					 u32 points_mask)

{

	int ret;
@@ -981,6 +981,70 @@ static void icl_force_disable_sagv(struct intel_display *display, 
	icl_pcode_restrict_qgv_points(display, bw_state->qgv_points_mask);

}



void icl_sagv_pre_plane_update(struct intel_atomic_state *state)

{

	struct intel_display *display = to_intel_display(state);

	const struct intel_bw_state *old_bw_state =

		intel_atomic_get_old_bw_state(state);

	const struct intel_bw_state *new_bw_state =

		intel_atomic_get_new_bw_state(state);

	u16 old_mask, new_mask;



	if (!new_bw_state)

		return;



	old_mask = old_bw_state->qgv_points_mask;

	new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;



	if (old_mask == new_mask)

		return;



	WARN_ON(!new_bw_state->base.changed);



	drm_dbg_kms(display->drm, "Restricting QGV points: 0x%x -> 0x%x\n",

		    old_mask, new_mask);



	/*

	 * Restrict required qgv points before updating the configuration.

	 * According to BSpec we can't mask and unmask qgv points at the same

	 * time. Also masking should be done before updating the configuration

	 * and unmasking afterwards.

	 */

	icl_pcode_restrict_qgv_points(display, new_mask);

}



void icl_sagv_post_plane_update(struct intel_atomic_state *state)

{

	struct intel_display *display = to_intel_display(state);

	const struct intel_bw_state *old_bw_state =

		intel_atomic_get_old_bw_state(state);

	const struct intel_bw_state *new_bw_state =

		intel_atomic_get_new_bw_state(state);

	u16 old_mask, new_mask;



	if (!new_bw_state)

		return;



	old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;

	new_mask = new_bw_state->qgv_points_mask;



	if (old_mask == new_mask)

		return;



	WARN_ON(!new_bw_state->base.changed);



	drm_dbg_kms(display->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",

		    old_mask, new_mask);



	/*

	 * Allow required qgv points after updating the configuration.

	 * According to BSpec we can't mask and unmask qgv points at the same

	 * time. Also masking should be done before updating the configuration

	 * and unmasking afterwards.

	 */

	icl_pcode_restrict_qgv_points(display, new_mask);

}



static int mtl_find_qgv_points(struct intel_display *display,

			       unsigned int data_rate,

			       unsigned int num_active_planes,

drivers/gpu/drm/i915/display/intel_bw.h

+2 −2
Original line number Diff line number Diff line
@@ -67,8 +67,6 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state); 
void intel_bw_init_hw(struct intel_display *display);

int intel_bw_init(struct intel_display *display);

int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms);

int icl_pcode_restrict_qgv_points(struct intel_display *display,

				  u32 points_mask);

int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,

			    bool *need_cdclk_calc);

int intel_bw_min_cdclk(struct intel_display *display,
@@ -79,5 +77,7 @@ void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc); 
bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state);

bool intel_bw_can_enable_sagv(struct intel_display *display,

			      const struct intel_bw_state *bw_state);

void icl_sagv_pre_plane_update(struct intel_atomic_state *state);

void icl_sagv_post_plane_update(struct intel_atomic_state *state);



#endif /* __INTEL_BW_H__ */

drivers/gpu/drm/i915/display/skl_watermark.c

+0 −64
Original line number Diff line number Diff line
@@ -265,70 +265,6 @@ static void skl_sagv_post_plane_update(struct intel_atomic_state *state) 
		skl_sagv_enable(display);

}



static void icl_sagv_pre_plane_update(struct intel_atomic_state *state)

{

	struct intel_display *display = to_intel_display(state);

	const struct intel_bw_state *old_bw_state =

		intel_atomic_get_old_bw_state(state);

	const struct intel_bw_state *new_bw_state =

		intel_atomic_get_new_bw_state(state);

	u16 old_mask, new_mask;



	if (!new_bw_state)

		return;



	old_mask = old_bw_state->qgv_points_mask;

	new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;



	if (old_mask == new_mask)

		return;



	WARN_ON(!new_bw_state->base.changed);



	drm_dbg_kms(display->drm, "Restricting QGV points: 0x%x -> 0x%x\n",

		    old_mask, new_mask);



	/*

	 * Restrict required qgv points before updating the configuration.

	 * According to BSpec we can't mask and unmask qgv points at the same

	 * time. Also masking should be done before updating the configuration

	 * and unmasking afterwards.

	 */

	icl_pcode_restrict_qgv_points(display, new_mask);

}



static void icl_sagv_post_plane_update(struct intel_atomic_state *state)

{

	struct intel_display *display = to_intel_display(state);

	const struct intel_bw_state *old_bw_state =

		intel_atomic_get_old_bw_state(state);

	const struct intel_bw_state *new_bw_state =

		intel_atomic_get_new_bw_state(state);

	u16 old_mask, new_mask;



	if (!new_bw_state)

		return;



	old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;

	new_mask = new_bw_state->qgv_points_mask;



	if (old_mask == new_mask)

		return;



	WARN_ON(!new_bw_state->base.changed);



	drm_dbg_kms(display->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",

		    old_mask, new_mask);



	/*

	 * Allow required qgv points after updating the configuration.

	 * According to BSpec we can't mask and unmask qgv points at the same

	 * time. Also masking should be done before updating the configuration

	 * and unmasking afterwards.

	 */

	icl_pcode_restrict_qgv_points(display, new_mask);

}



void intel_sagv_pre_plane_update(struct intel_atomic_state *state)

{

	struct intel_display *display = to_intel_display(state);