Commit 9a1c58cf authored by Oliver Upton's avatar Oliver Upton
Browse files

KVM: arm64: nv: Adjust range of accessible PMCs according to HPMN 



The value of MDCR_EL2.HPMN controls the number of event counters made
visible to EL0 and EL1. This means it is possible for the guest
hypervisor to allow direct access to event counters to the L2.

Rework KVM's PMU register emulation to take the effects of HPMN into
account when handling a trap. For bitmask-style registers, writes only
affect accessible registers.

Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241025182354.3364124-14-oliver.upton@linux.dev


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent a3034dab

arch/arm64/kvm/pmu-emul.c

+13 −1
Original line number Diff line number Diff line
@@ -283,6 +283,18 @@ bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu, unsigned int idx) 
	return idx >= hpmn;

}



u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *vcpu)

{

	u64 mask = kvm_pmu_implemented_counter_mask(vcpu);

	u64 hpmn;



	if (!vcpu_has_nv(vcpu) || vcpu_is_el2(vcpu))

		return mask;



	hpmn = SYS_FIELD_GET(MDCR_EL2, HPMN, __vcpu_sys_reg(vcpu, MDCR_EL2));

	return mask & ~GENMASK(vcpu->kvm->arch.pmcr_n - 1, hpmn);

}



u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu)

{

	u64 val = FIELD_GET(ARMV8_PMU_PMCR_N, kvm_vcpu_read_pmcr(vcpu));
@@ -592,7 +604,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) 
		kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);



	if (val & ARMV8_PMU_PMCR_P) {

		unsigned long mask = kvm_pmu_implemented_counter_mask(vcpu);

		unsigned long mask = kvm_pmu_accessible_counter_mask(vcpu);

		mask &= ~BIT(ARMV8_PMU_CYCLE_IDX);

		for_each_set_bit(i, &mask, 32)

			kvm_pmu_set_pmc_value(kvm_vcpu_idx_to_pmc(vcpu, i), 0, true);

arch/arm64/kvm/sys_regs.c

+6 −6
Original line number Diff line number Diff line
@@ -1168,7 +1168,7 @@ static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 va 
{

	bool set;



	val &= kvm_pmu_implemented_counter_mask(vcpu);

	val &= kvm_pmu_accessible_counter_mask(vcpu);



	switch (r->reg) {

	case PMOVSSET_EL0:
@@ -1191,7 +1191,7 @@ static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 va 


static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val)

{

	u64 mask = kvm_pmu_implemented_counter_mask(vcpu);

	u64 mask = kvm_pmu_accessible_counter_mask(vcpu);



	*val = __vcpu_sys_reg(vcpu, r->reg) & mask;

	return 0;
@@ -1205,7 +1205,7 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
	if (pmu_access_el0_disabled(vcpu))

		return false;



	mask = kvm_pmu_implemented_counter_mask(vcpu);

	mask = kvm_pmu_accessible_counter_mask(vcpu);

	if (p->is_write) {

		val = p->regval & mask;

		if (r->Op2 & 0x1) {
@@ -1228,7 +1228,7 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,

			   const struct sys_reg_desc *r)

{

	u64 mask = kvm_pmu_implemented_counter_mask(vcpu);

	u64 mask = kvm_pmu_accessible_counter_mask(vcpu);



	if (check_pmu_access_disabled(vcpu, 0))

		return false;
@@ -1252,7 +1252,7 @@ static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,

			 const struct sys_reg_desc *r)

{

	u64 mask = kvm_pmu_implemented_counter_mask(vcpu);

	u64 mask = kvm_pmu_accessible_counter_mask(vcpu);



	if (pmu_access_el0_disabled(vcpu))

		return false;
@@ -1282,7 +1282,7 @@ static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
	if (pmu_write_swinc_el0_disabled(vcpu))

		return false;



	mask = kvm_pmu_implemented_counter_mask(vcpu);

	mask = kvm_pmu_accessible_counter_mask(vcpu);

	kvm_pmu_software_increment(vcpu, p->regval & mask);

	return true;

}

include/kvm/arm_pmu.h

+5 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ static __always_inline bool kvm_arm_support_pmu_v3(void) 
u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);

void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);

u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu);

u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *vcpu);

u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1);

void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu);

void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
@@ -118,6 +119,10 @@ static inline u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu) 
{

	return 0;

}

static inline u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *vcpu)

{

	return 0;

}

static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {}

static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}

static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}