Commit 9a683fe0 authored by Namhyung Kim's avatar Namhyung Kim
Browse files

Merge tag 'v7.0-rc6' into perf-tools 



To get the latest updates and fixes.

Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
parents 841dbf48 7aaa8047

.mailmap

+2 −0
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@@ -316,6 +316,7 @@ Hans Verkuil <hverkuil@kernel.org> <hverkuil-cisco@xs4all.nl> 
Hans Verkuil <hverkuil@kernel.org> <hansverk@cisco.com>

Hao Ge <hao.ge@linux.dev> <gehao@kylinos.cn>

Harry Yoo <harry.yoo@oracle.com> <42.hyeyoo@gmail.com>

Harry Yoo <harry@kernel.org> <harry.yoo@oracle.com>

Heiko Carstens <hca@linux.ibm.com> <h.carstens@de.ibm.com>

Heiko Carstens <hca@linux.ibm.com> <heiko.carstens@de.ibm.com>

Heiko Stuebner <heiko@sntech.de> <heiko.stuebner@bqreaders.com>
@@ -587,6 +588,7 @@ Morten Welinder <terra@gnome.org> 
Morten Welinder <welinder@anemone.rentec.com>

Morten Welinder <welinder@darter.rentec.com>

Morten Welinder <welinder@troll.com>

Muhammad Usama Anjum <usama.anjum@arm.com> <usama.anjum@collabora.com>

Mukesh Ojha <quic_mojha@quicinc.com> <mojha@codeaurora.org>

Muna Sinada <quic_msinada@quicinc.com> <msinada@codeaurora.org>

Murali Nalajala <quic_mnalajal@quicinc.com> <mnalajal@codeaurora.org>

Documentation/PCI/pcieaer-howto.rst

+10 −0
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@@ -85,6 +85,16 @@ In the example, 'Requester ID' means the ID of the device that sent 
the error message to the Root Port. Please refer to PCIe specs for other

fields.



The 'TLP Header' is the prefix/header of the TLP that caused the error

in raw hex format. To decode the TLP Header into human-readable form

one may use tlp-tool:



https://github.com/mmpg-x86/tlp-tool



Example usage::



  curl -L https://git.kernel.org/linus/2ca1c94ce0b6 | rtlp-tool --aer



AER Ratelimits

--------------

Documentation/core-api/dma-attributes.rst

+30 −8
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@@ -149,11 +149,33 @@ For architectures that require cache flushing for DMA coherence 
DMA_ATTR_MMIO will not perform any cache flushing. The address

provided must never be mapped cacheable into the CPU.



DMA_ATTR_CPU_CACHE_CLEAN

------------------------



This attribute indicates the CPU will not dirty any cacheline overlapping this

DMA_FROM_DEVICE/DMA_BIDIRECTIONAL buffer while it is mapped. This allows

multiple small buffers to safely share a cacheline without risk of data

corruption, suppressing DMA debug warnings about overlapping mappings.

All mappings sharing a cacheline should have this attribute.
 
DMA_ATTR_DEBUGGING_IGNORE_CACHELINES

------------------------------------



This attribute indicates that CPU cache lines may overlap for buffers mapped

with DMA_FROM_DEVICE or DMA_BIDIRECTIONAL.



Such overlap may occur when callers map multiple small buffers that reside

within the same cache line. In this case, callers must guarantee that the CPU

will not dirty these cache lines after the mappings are established. When this

condition is met, multiple buffers can safely share a cache line without risking

data corruption.



All mappings that share a cache line must set this attribute to suppress DMA

debug warnings about overlapping mappings.



DMA_ATTR_REQUIRE_COHERENT

-------------------------



DMA mapping requests with the DMA_ATTR_REQUIRE_COHERENT fail on any

system where SWIOTLB or cache management is required. This should only

be used to support uAPI designs that require continuous HW DMA

coherence with userspace processes, for example RDMA and DRM. At a

minimum the memory being mapped must be userspace memory from

pin_user_pages() or similar.



Drivers should consider using dma_mmap_pages() instead of this

interface when building their uAPIs, when possible.



It must never be used in an in-kernel driver that only works with

kernel memory.

Documentation/devicetree/bindings/mtd/st,spear600-smi.yaml

+19 −7
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@@ -19,9 +19,6 @@ description: 
  Flash sub nodes describe the memory range and optional per-flash

  properties.



allOf:

  - $ref: mtd.yaml#



properties:

  compatible:

    const: st,spear600-smi
@@ -42,14 +39,29 @@ properties: 
    $ref: /schemas/types.yaml#/definitions/uint32

    description: Functional clock rate of the SMI controller in Hz.



patternProperties:

  "^flash@.*$":

    $ref: /schemas/mtd/mtd.yaml#



    properties:

      reg:

        maxItems: 1



      st,smi-fast-mode:

        type: boolean

        description: Indicates that the attached flash supports fast read mode.



    unevaluatedProperties: false



    required:

      - reg



required:

  - compatible

  - reg

  - clock-rate

  - "#address-cells"

  - "#size-cells"



unevaluatedProperties: false
@@ -64,7 +76,7 @@ examples: 
        interrupts = <12>;

        clock-rate = <50000000>;  /* 50 MHz */



        flash@f8000000 {

        flash@fc000000 {

            reg = <0xfc000000 0x1000>;

            st,smi-fast-mode;

        };

Documentation/devicetree/bindings/regulator/regulator.yaml

+2 −2
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@@ -168,7 +168,7 @@ properties: 
      offset from voltage set to regulator.



  regulator-uv-protection-microvolt:

    description: Set over under voltage protection limit. This is a limit where

    description: Set under voltage protection limit. This is a limit where

      hardware performs emergency shutdown. Zero can be passed to disable

      protection and value '1' indicates that protection should be enabled but

      limit setting can be omitted. Limit is given as microvolt offset from
@@ -182,7 +182,7 @@ properties: 
      is given as microvolt offset from voltage set to regulator.



  regulator-uv-warn-microvolt:

    description: Set over under voltage warning limit. This is a limit where

    description: Set under voltage warning limit. This is a limit where

      hardware is assumed still to be functional but approaching limit where

      it gets damaged. Recovery actions should be initiated. Zero can be passed

      to disable detection and value '1' indicates that detection should