Commit 9aa3face authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/gr/gf100-: switch to newer style interrupt handler 



Ampere.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent 1a344688

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

+21 −6
Original line number Diff line number Diff line
@@ -1600,10 +1600,10 @@ gf100_gr_ctxctl_isr(struct gf100_gr *gr) 
	}

}



static void

gf100_gr_intr(struct nvkm_gr *base)

static irqreturn_t

gf100_gr_intr(struct nvkm_inth *inth)

{

	struct gf100_gr *gr = gf100_gr(base);

	struct gf100_gr *gr = container_of(inth, typeof(*gr), base.engine.subdev.inth);

	struct nvkm_subdev *subdev = &gr->base.engine.subdev;

	struct nvkm_device *device = subdev->device;

	struct nvkm_chan *chan;
@@ -1690,6 +1690,7 @@ gf100_gr_intr(struct nvkm_gr *base) 


	nvkm_wr32(device, 0x400500, 0x00010001);

	nvkm_chan_put(&chan, flags);

	return IRQ_HANDLED;

}



static void
@@ -1985,8 +1986,15 @@ gf100_gr_oneinit(struct nvkm_gr *base) 
	struct gf100_gr *gr = gf100_gr(base);

	struct nvkm_subdev *subdev = &gr->base.engine.subdev;

	struct nvkm_device *device = subdev->device;

	struct nvkm_intr *intr = &device->mc->intr;

	enum nvkm_intr_type intr_type = NVKM_INTR_SUBDEV;

	int ret, i, j;



	ret = nvkm_inth_add(intr, intr_type, NVKM_INTR_PRIO_NORMAL, &gr->base.engine.subdev,

			    gf100_gr_intr, &gr->base.engine.subdev.inth);

	if (ret)

		return ret;



	nvkm_pmu_pgob(device->pmu, false);



	gr->rop_nr = gr->func->rops(gr);
@@ -2047,7 +2055,7 @@ gf100_gr_init_(struct nvkm_gr *base) 
	struct nvkm_subdev *subdev = &base->engine.subdev;

	struct nvkm_device *device = subdev->device;

	bool reset = device->chipset == 0x137 || device->chipset == 0x138;

	u32 ret;

	int ret;



	/* On certain GP107/GP108 boards, we trigger a weird issue where

	 * GR will stop responding to PRI accesses after we've asked the
@@ -2083,7 +2091,12 @@ gf100_gr_init_(struct nvkm_gr *base) 
	if (ret)

		return ret;



	return gr->func->init(gr);

	ret = gr->func->init(gr);

	if (ret)

		return ret;



	nvkm_inth_allow(&subdev->inth);

	return 0;

}



static int
@@ -2091,6 +2104,9 @@ gf100_gr_fini(struct nvkm_gr *base, bool suspend) 
{

	struct gf100_gr *gr = gf100_gr(base);

	struct nvkm_subdev *subdev = &gr->base.engine.subdev;



	nvkm_inth_block(&subdev->inth);



	nvkm_falcon_put(&gr->gpccs.falcon, subdev);

	nvkm_falcon_put(&gr->fecs.falcon, subdev);

	return 0;
@@ -2457,7 +2473,6 @@ gf100_gr_ = { 
	.init = gf100_gr_init_,

	.fini = gf100_gr_fini,

	.reset = gf100_gr_reset,

	.intr = gf100_gr_intr,

	.units = gf100_gr_units,

	.chan_new = gf100_gr_chan_new,

	.object_get = gf100_gr_object_get,

drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ gf100_mc_intrs[] = { 
	{ NVKM_ENGINE_DISP    , 0, 0, 0x04000000, true },

	{ NVKM_ENGINE_MSPDEC  , 0, 0, 0x00020000, true },

	{ NVKM_ENGINE_MSVLD   , 0, 0, 0x00008000, true },

	{ NVKM_ENGINE_GR      , 0, 0, 0x00001000, true },

	{ NVKM_ENGINE_GR      , 0, 0, 0x00001000 },

	{ NVKM_ENGINE_FIFO    , 0, 0, 0x00000100 },

	{ NVKM_ENGINE_CE      , 1, 0, 0x00000040, true },

	{ NVKM_ENGINE_CE      , 0, 0, 0x00000020, true },

drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c

+2 −1
Original line number Diff line number Diff line
@@ -43,7 +43,8 @@ gk104_mc_intrs[] = { 
	{ NVKM_SUBDEV_I2C     , 0, 0, 0x00200000, true },

	{ NVKM_SUBDEV_TIMER   , 0, 0, 0x00100000, true },

	{ NVKM_SUBDEV_THERM   , 0, 0, 0x00040000, true },

	{ NVKM_SUBDEV_TOP     , 0, 0, 0xffffffff, true },

	{ NVKM_SUBDEV_TOP     , 0, 0, 0x00001000 },

	{ NVKM_SUBDEV_TOP     , 0, 0, 0xffffefff, true },

	{},

};

drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c

+2 −2
Original line number Diff line number Diff line
@@ -37,8 +37,8 @@ gp100_mc_intrs[] = { 
	{ NVKM_SUBDEV_I2C     , 0, 0, 0x00200000, true },

	{ NVKM_SUBDEV_TIMER   , 0, 0, 0x00100000, true },

	{ NVKM_SUBDEV_THERM   , 0, 0, 0x00040000, true },

	{ NVKM_SUBDEV_TOP     , 0, 0, 0x00008000 },

	{ NVKM_SUBDEV_TOP     , 0, 0, 0xffff7fff, true },

	{ NVKM_SUBDEV_TOP     , 0, 0, 0x00009000 },

	{ NVKM_SUBDEV_TOP     , 0, 0, 0xffff6fff, true },

	{},

};