Commit 9b0ed33a authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Jakub Kicinski
Browse files

net: stmmac: mdio: merge stmmac_mdio_read() and stmmac_mdio_write() 



stmmac_mdio_read() and stmmac_mdio_write() are virtually identical
except for the final read in the stmmac_mdio_read(). Handle this as
a flag.

Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Tested-by: default avatarMohd Ayaan Anwar <quic_mohdayaa@quicinc.com>
Link: https://patch.msgid.link/E1uu8oC-00000001vos-2JnA@rmk-PC.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 6cb3d67a

drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c

+24 −35
Original line number Diff line number Diff line
@@ -240,29 +240,41 @@ static u32 stmmac_mdio_format_addr(struct stmmac_priv *priv, 
	       MII_BUSY;

}



static int stmmac_mdio_read(struct stmmac_priv *priv, unsigned int pa,

			    unsigned int gr, u32 cmd, int data)

static int stmmac_mdio_access(struct stmmac_priv *priv, unsigned int pa,

			      unsigned int gr, u32 cmd, u32 data, bool read)

{

	unsigned int mii_address = priv->hw->mii.addr;

	unsigned int mii_data = priv->hw->mii.data;

	u32 value;

	void __iomem *mii_address = priv->ioaddr + priv->hw->mii.addr;

	void __iomem *mii_data = priv->ioaddr + priv->hw->mii.data;

	u32 addr;

	int ret;



	ret = stmmac_mdio_wait(priv->ioaddr + mii_address, MII_BUSY);

	ret = stmmac_mdio_wait(mii_address, MII_BUSY);

	if (ret)

		return ret;



	value = stmmac_mdio_format_addr(priv, pa, gr) | cmd;

	addr = stmmac_mdio_format_addr(priv, pa, gr) | cmd;



	writel(data, priv->ioaddr + mii_data);

	writel(value, priv->ioaddr + mii_address);

	writel(data, mii_data);

	writel(addr, mii_address);



	ret = stmmac_mdio_wait(priv->ioaddr + mii_address, MII_BUSY);

	ret = stmmac_mdio_wait(mii_address, MII_BUSY);

	if (ret)

		return ret;



	/* Read the data from the MII data register */

	return readl(priv->ioaddr + mii_data) & MII_DATA_MASK;

	/* Read the data from the MII data register if in read mode */

	return read ? readl(mii_data) & MII_DATA_MASK : 0;

}



static int stmmac_mdio_read(struct stmmac_priv *priv, unsigned int pa,

			    unsigned int gr, u32 cmd, int data)

{

	return stmmac_mdio_access(priv, pa, gr, cmd, data, true);

}



static int stmmac_mdio_write(struct stmmac_priv *priv, unsigned int pa,

			     unsigned int gr, u32 cmd, int data)

{

	return stmmac_mdio_access(priv, pa, gr, cmd, data, false);

}



/**
@@ -330,29 +342,6 @@ static int stmmac_mdio_read_c45(struct mii_bus *bus, int phyaddr, int devad, 
	return data;

}



static int stmmac_mdio_write(struct stmmac_priv *priv, unsigned int pa,

			     unsigned int gr, u32 cmd, int data)

{

	unsigned int mii_address = priv->hw->mii.addr;

	unsigned int mii_data = priv->hw->mii.data;

	u32 value;

	int ret;



	/* Wait until any existing MII operation is complete */

	ret = stmmac_mdio_wait(priv->ioaddr + mii_address, MII_BUSY);

	if (ret)

		return ret;



	value = stmmac_mdio_format_addr(priv, pa, gr) | cmd;



	/* Set the MII address register to write */

	writel(data, priv->ioaddr + mii_data);

	writel(value, priv->ioaddr + mii_address);



	/* Wait until any existing MII operation is complete */

	return stmmac_mdio_wait(priv->ioaddr + mii_address, MII_BUSY);

}



/**

 * stmmac_mdio_write_c22

 * @bus: points to the mii_bus structure